Merge branch 'master' of https://github.com/mossmann/hackrf
This commit is contained in:
Jared Boone
@ -41,9 +41,6 @@ void rffc5071_init(void)
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gpio_set(PORT_MIXER, PIN_MIXER_ENX); /* active low */
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gpio_clear(PORT_MIXER, (PIN_MIXER_SCLK | PIN_MIXER_SDATA));
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//FIXME no writes until we get reads sorted:
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return;
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//FIXME hard coded setup, fields not broken out
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/* initial setup */
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rffc5071_reg_write(RFFC5071_P2_FREQ1, 0x0000);
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@ -59,9 +56,9 @@ void rffc5071_init(void)
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rffc5071_reg_write(RFFC5071_MIX_CONT, 0x4800); /* half duplex */
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/*
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* setup for 2 GHz LO:
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* n_lo = 1
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* lodiv = 2
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* setup for 250 MHz LO:
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* n_lo = 4
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* lodiv = 16 (2^4, so set to 4)
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* fvco = 4 GHz
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* fbkdiv = 4
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* ndiv = 20
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@ -69,11 +66,178 @@ void rffc5071_init(void)
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* nummsb = 0
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* numlsb = 0
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*/
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rffc5071_reg_write(RFFC5071_P1_FREQ1, 0x0a28);
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//rffc5071_reg_write(RFFC5071_P1_FREQ1, 0x0a48);
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//rffc5071_reg_write(RFFC5071_P1_FREQ2, 0x0000);
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//rffc5071_reg_write(RFFC5071_P1_FREQ3, 0x0000);
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/* charge pump set for VCO > 3.2 GHz */
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//rffc5071_reg_write(RFFC5071_LF, 0xbefb);
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/*
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* setup for 400 MHz LO:
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* lodiv = 8 (2^3, so set to 3)
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* fvco = 3200 MHz
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* fbkdiv = 2
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* ndiv = 32
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* n = 32
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* nummsb = 0
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* numlsb = 0
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*/
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//rffc5071_reg_write(RFFC5071_P1_FREQ1, 0x1034);
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//rffc5071_reg_write(RFFC5071_P1_FREQ2, 0x0000);
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//rffc5071_reg_write(RFFC5071_P1_FREQ3, 0x0000);
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/*
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* setup for 500 MHz LO:
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* n_lo = 3
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* lodiv = 8 (2^3, so set to 3)
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* fvco = 4 GHz
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* fbkdiv = 4
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* ndiv = 20
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* n = 20
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* nummsb = 0
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* numlsb = 0
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*/
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rffc5071_reg_write(RFFC5071_P1_FREQ1, 0x0a39);
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rffc5071_reg_write(RFFC5071_P1_FREQ2, 0x0000);
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rffc5071_reg_write(RFFC5071_P1_FREQ3, 0x0000);
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/* charge pump set for VCO > 3.2 GHz */
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rffc5071_reg_write(RFFC5071_LF, 0xBEFB);
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rffc5071_reg_write(RFFC5071_LF, 0xbefb);
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/*
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* setup for 513 MHz LO:
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* n_lo = 3
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* lodiv = 8 (2^3, so set to 3)
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* fvco = 4104 MHz
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* fbkdiv = 4
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* ndiv = 20.52
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* n = 20
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* nummsb = 34078 (0x851e)
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* numlsb = 184 (0xb8)
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*/
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//rffc5071_reg_write(RFFC5071_P1_FREQ1, 0x0a38);
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//rffc5071_reg_write(RFFC5071_P1_FREQ2, 0x851e);
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//rffc5071_reg_write(RFFC5071_P1_FREQ3, 0xb800);
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/* charge pump set for VCO > 3.2 GHz */
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//rffc5071_reg_write(RFFC5071_LF, 0xbefb);
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/*
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* setup for 1 GHz LO:
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* n_lo = 2
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* lodiv = 4 (2^2, so set to 2)
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* fvco = 4 GHz
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* fbkdiv = 4
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* ndiv = 20
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* n = 20
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* nummsb = 0
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* numlsb = 0
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*/
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//rffc5071_reg_write(RFFC5071_P1_FREQ1, 0x0a29);
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//rffc5071_reg_write(RFFC5071_P1_FREQ2, 0x0000);
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//rffc5071_reg_write(RFFC5071_P1_FREQ3, 0x0000);
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/* charge pump set for VCO > 3.2 GHz */
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//rffc5071_reg_write(RFFC5071_LF, 0xbefb);
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/*
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* setup for 1417 MHz LO:
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* n_lo = 1
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* lodiv = 2 (2^1, so set to 1)
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* fvco = 2834 MHz
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* fbkdiv = 2
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* ndiv = 28.34
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* n = 28
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* nummsb = 22282 (570a)
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* numlsb = 61 (0x3d)
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*/
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//rffc5071_reg_write(RFFC5071_P1_FREQ1, 0x0e14);
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//rffc5071_reg_write(RFFC5071_P1_FREQ2, 0x570a);
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//rffc5071_reg_write(RFFC5071_P1_FREQ3, 0x3d00);
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/* charge pump set for VCO > 3.2 GHz */
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//rffc5071_reg_write(RFFC5071_LF, 0xbefb);
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/*
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* setup for 2 GHz LO:
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* n_lo = 1
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* lodiv = 2 (2^1, so set to 1)
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* fvco = 4 GHz
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* fbkdiv = 4
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* ndiv = 20
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* n = 20
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* nummsb = 0
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* numlsb = 0
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*/
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//rffc5071_reg_write(RFFC5071_P1_FREQ1, 0x0a19);
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//rffc5071_reg_write(RFFC5071_P1_FREQ2, 0x0000);
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//rffc5071_reg_write(RFFC5071_P1_FREQ3, 0x0000);
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/* charge pump set for VCO > 3.2 GHz */
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//rffc5071_reg_write(RFFC5071_LF, 0xbefb);
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/*
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* setup for 2191 GHz LO:
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* n_lo = 1
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* lodiv = 2 (2^1, so set to 1)
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* fvco = 4382 MHz
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* fbkdiv = 4
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* ndiv = 21.91
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* n = 21
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* nummsb = 59637 (0xe8f5)
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* numlsb = 194 (0xc2)
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*/
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//rffc5071_reg_write(RFFC5071_P1_FREQ1, 0x0a98);
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//rffc5071_reg_write(RFFC5071_P1_FREQ2, 0xe8f5);
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//rffc5071_reg_write(RFFC5071_P1_FREQ3, 0xc200);
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/* charge pump set for VCO > 3.2 GHz */
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//rffc5071_reg_write(RFFC5071_LF, 0xbefb);
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/*
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* setup for 2341 GHz LO:
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* n_lo = 1
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* lodiv = 2 (2^1, so set to 1)
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* fvco = 4682 MHz
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* fbkdiv = 4
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* ndiv = 23.41
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* n = 23
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* nummsb = 26869 (0x68f5)
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* numlsb = 194 (0xc2)
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*/
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//rffc5071_reg_write(RFFC5071_P1_FREQ1, 0x0b9a);
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//rffc5071_reg_write(RFFC5071_P1_FREQ2, 0x68f5);
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//rffc5071_reg_write(RFFC5071_P1_FREQ3, 0xc200);
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/* charge pump set for VCO > 3.2 GHz */
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//rffc5071_reg_write(RFFC5071_LF, 0xbefb);
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/*
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* setup for 2341 GHz LO:
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* n_lo = 1
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* lodiv = 2 (2^1, so set to 1)
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* fvco = 4782 MHz
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* fbkdiv = 4
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* ndiv = 23.91
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* n = 23
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* nummsb = 59637 (0xe8f5)
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* numlsb = 194 (0xc2)
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*/
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//rffc5071_reg_write(RFFC5071_P1_FREQ1, 0x0b9a);
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//rffc5071_reg_write(RFFC5071_P1_FREQ2, 0xe8f5);
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//rffc5071_reg_write(RFFC5071_P1_FREQ3, 0xc200);
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/* charge pump set for VCO > 3.2 GHz */
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//rffc5071_reg_write(RFFC5071_LF, 0xbefb);
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/*
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* setup for 2411 GHz LO:
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* n_lo = 1
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* lodiv = 2 (2^1, so set to 1)
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* fvco = 4822 MHz
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* fbkdiv = 4
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* ndiv = 24.11
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* n = 24
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* nummsb = 7208 (0x1c28)
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* numlsb = 245 (0xf5)
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*/
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//rffc5071_reg_write(RFFC5071_P1_FREQ1, 0x0c18);
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//rffc5071_reg_write(RFFC5071_P1_FREQ2, 0x1c28);
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//rffc5071_reg_write(RFFC5071_P1_FREQ3, 0xf500);
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/* charge pump set for VCO > 3.2 GHz */
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//rffc5071_reg_write(RFFC5071_LF, 0xbefb);
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/* enable device */
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rffc5071_reg_write(RFFC5071_SDI_CTRL, 0xc000); /* mixer 1 (TX) */
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@ -104,11 +268,25 @@ void rffc5071_reg_write(uint8_t reg, uint16_t val)
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/* make sure everything is starting in the correct state */
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gpio_set(PORT_MIXER, PIN_MIXER_ENX);
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gpio_clear(PORT_MIXER, (PIN_MIXER_SCLK | PIN_MIXER_SDATA));
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/*
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* The device requires two clocks while ENX is high before a serial
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* transaction. This is not clearly documented.
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*/
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serial_delay();
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gpio_set(PORT_MIXER, PIN_MIXER_SCLK);
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serial_delay();
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gpio_clear(PORT_MIXER, PIN_MIXER_SCLK);
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serial_delay();
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gpio_set(PORT_MIXER, PIN_MIXER_SCLK);
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serial_delay();
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gpio_clear(PORT_MIXER, PIN_MIXER_SCLK);
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/* start transaction by bringing ENX low */
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gpio_clear(PORT_MIXER, PIN_MIXER_ENX);
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serial_delay();
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while (bits--) {
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if (data & msb)
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@ -144,11 +322,25 @@ uint16_t rffc5071_reg_read(uint8_t reg)
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/* make sure everything is starting in the correct state */
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gpio_set(PORT_MIXER, PIN_MIXER_ENX);
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gpio_clear(PORT_MIXER, (PIN_MIXER_SCLK | PIN_MIXER_SDATA));
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/*
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* The device requires two clocks while ENX is high before a serial
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* transaction. This is not clearly documented.
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*/
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serial_delay();
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gpio_set(PORT_MIXER, PIN_MIXER_SCLK);
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serial_delay();
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gpio_clear(PORT_MIXER, PIN_MIXER_SCLK);
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serial_delay();
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gpio_set(PORT_MIXER, PIN_MIXER_SCLK);
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serial_delay();
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gpio_clear(PORT_MIXER, PIN_MIXER_SCLK);
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/* start transaction by bringing ENX low */
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gpio_clear(PORT_MIXER, PIN_MIXER_ENX);
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serial_delay();
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while (bits--) {
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if (data & msb)
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@ -68,18 +68,9 @@ int main(void)
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ssp1_set_mode_max2837();
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max2837_setup();
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rffc5071_init();
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rffc5071_reg_write(RFFC5071_GPO, 0x0001); /* PLL lock output on GPO4 */
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gpio_set(PORT_LED1_3, (PIN_LED2)); /* LED2 on */
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/* FIXME testing serial reads */
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while (1) {
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//rffc5071_init();
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//rffc5071_reg_write(0x7a, 0xf0ca);
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if (rffc5071_reg_read(0x00) == 0xbefb)
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gpio_set(PORT_LED1_3, (PIN_LED3)); /* LED3 on */
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else
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gpio_clear(PORT_LED1_3, (PIN_LED3)); /* LED3 off */
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}
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max2837_set_frequency(freq);
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max2837_start();
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max2837_tx();
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