From d9884af8b8d04fdfb177aa80341b223c5c91435f Mon Sep 17 00:00:00 2001
From: Jared Boone <jboone@earfeast.com>
Date: Sat, 11 May 2013 12:11:37 -0700
Subject: [PATCH] PLL1 was misconfigured to run at 408MHz (way out of spec)
 instead of 204MHz. Corrected this by using DIRECT=1 instead of FBSEL=1.

---
 firmware/common/hackrf_core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/firmware/common/hackrf_core.c b/firmware/common/hackrf_core.c
index b94fc967..f2abd656 100644
--- a/firmware/common/hackrf_core.c
+++ b/firmware/common/hackrf_core.c
@@ -252,7 +252,7 @@ void cpu_clock_init(void)
             | CGU_PLL1_CTRL_PSEL(0)
             | CGU_PLL1_CTRL_NSEL(0)
 			| CGU_PLL1_CTRL_MSEL(16)
-			| CGU_PLL1_CTRL_FBSEL;
+			| CGU_PLL1_CTRL_DIRECT;
 
 	/* wait until stable */
 	while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK));