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Adjusted cpu_clock_pll1_low_speed() to operate at 48MHz, as per several comments with the code. The actual MSEL value was previously selecting 84MHz.

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This commit is contained in:
Jared Boone
2013-09-04 16:23:32 -07:00
parent 237bf6ecdb
commit d76d72665e
1 changed files with 2 additions and 2 deletions
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4
firmware/common/hackrf_core.c
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@ -403,11 +403,11 @@ void cpu_clock_pll1_low_speed(void)
CGU_PLL1_CTRL_BYPASS | /* BYPASS */ CGU_PLL1_CTRL_BYPASS | /* BYPASS */
CGU_PLL1_CTRL_DIRECT | /* DIRECT */ CGU_PLL1_CTRL_DIRECT | /* DIRECT */
CGU_PLL1_CTRL_PSEL_MASK | CGU_PLL1_CTRL_MSEL_MASK | CGU_PLL1_CTRL_NSEL_MASK ); /* PSEL, MSEL, NSEL- divider ratios */ CGU_PLL1_CTRL_PSEL_MASK | CGU_PLL1_CTRL_MSEL_MASK | CGU_PLL1_CTRL_NSEL_MASK ); /* PSEL, MSEL, NSEL- divider ratios */
/* Set PLL1 up to 12MHz * 7 = 48MHz. */ /* Set PLL1 up to 12MHz * 4 = 48MHz. */
pll_reg |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL) pll_reg |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL)
| CGU_PLL1_CTRL_PSEL(0) | CGU_PLL1_CTRL_PSEL(0)
| CGU_PLL1_CTRL_NSEL(0) | CGU_PLL1_CTRL_NSEL(0)
| CGU_PLL1_CTRL_MSEL(6) | CGU_PLL1_CTRL_MSEL(3)
| CGU_PLL1_CTRL_FBSEL | CGU_PLL1_CTRL_FBSEL
| CGU_PLL1_CTRL_DIRECT; | CGU_PLL1_CTRL_DIRECT;
CGU_PLL1_CTRL = pll_reg; CGU_PLL1_CTRL = pll_reg;