From d68036f79d4b87337084b318b233e1aaffb56748 Mon Sep 17 00:00:00 2001
From: Jared Boone <jboone@earfeast.com>
Date: Thu, 14 Jun 2012 19:08:20 -0700
Subject: [PATCH] Eliminate ill-conceived HOST_CLK from CPLD. Rearrange clocks
 to not use AC-coupled CLK1 from Si5351C. Move CODEC_CLK to GCLK1,
 CODEC_X2_CLK (now HOST_CLK, too) to GCLK2. Add trace on Jellybean PCB to
 connect GCLK2 to LPC4330 pin 56 (P1_12) -- a different SGPIO8.

---
 hardware/jellybean/sgpio_if/top.ucf    | 8 ++++----
 hardware/jellybean/sgpio_if/top.vhd    | 7 -------
 hardware/jellybean/sgpio_if/top_tb.vhd | 7 ++-----
 3 files changed, 6 insertions(+), 16 deletions(-)

diff --git a/hardware/jellybean/sgpio_if/top.ucf b/hardware/jellybean/sgpio_if/top.ucf
index d57851ca..a593ec52 100755
--- a/hardware/jellybean/sgpio_if/top.ucf
+++ b/hardware/jellybean/sgpio_if/top.ucf
@@ -18,9 +18,9 @@
 # the Free Software Foundation, Inc., 51 Franklin Street,
 # Boston, MA 02110-1301, USA.
 
-NET "CODEC_CLK"    LOC="22" |FAST |IOSTANDARD=LVCMOS18;
-NET "CODEC_X2_CLK" LOC="23" |FAST |IOSTANDARD=LVCMOS18;
-#NET "GCLK2" LOC="27" |FAST |IOSTANDARD=LVCMOS18;
+NET "CODEC_CLK"    LOC="23" |FAST |IOSTANDARD=LVCMOS18;
+NET "CODEC_X2_CLK" LOC="27" |FAST |IOSTANDARD=LVCMOS18;
+#NET "GCLK0" LOC="22" |FAST |IOSTANDARD=LVCMOS18;
 
 NET "CODEC_X2_CLK" TNM_NET = CODEC_X2_CLK;
 TIMESPEC TS_codec_x2_data = PERIOD "CODEC_X2_CLK" 50 ns;
@@ -61,7 +61,7 @@ NET "B1AUX<9>"  LOC="49" |FAST |IOSTANDARD=LVCMOS18;
 NET "HOST_DIRECTION" LOC="71" |FAST |IOSTANDARD=LVCMOS33;
 NET "HOST_DISABLE"   LOC="76" |FAST |IOSTANDARD=LVCMOS33;
 NET "HOST_CAPTURE"   LOC="91" |FAST |IOSTANDARD=LVCMOS33;
-NET "HOST_CLK"       LOC="68" |FAST |IOSTANDARD=LVCMOS33;
+#NET "HOST_CLK"       LOC="68" |FAST |IOSTANDARD=LVCMOS33;
 NET "HOST_DATA<7>"   LOC="77" |FAST |IOSTANDARD=LVCMOS33;
 NET "HOST_DATA<6>"   LOC="61" |FAST |IOSTANDARD=LVCMOS33;
 NET "HOST_DATA<5>"   LOC="64" |FAST |IOSTANDARD=LVCMOS33;
diff --git a/hardware/jellybean/sgpio_if/top.vhd b/hardware/jellybean/sgpio_if/top.vhd
index 0127d1e2..31a61d0d 100755
--- a/hardware/jellybean/sgpio_if/top.vhd
+++ b/hardware/jellybean/sgpio_if/top.vhd
@@ -27,7 +27,6 @@ use UNISIM.vcomponents.all;
 entity top is
     Port(
         HOST_DATA       : inout std_logic_vector(7 downto 0);
-        HOST_CLK        : out   std_logic;
         HOST_CAPTURE    : out   std_logic;
         HOST_DISABLE    : in    std_logic;
         HOST_DIRECTION  : in    std_logic;
@@ -50,7 +49,6 @@ architecture Behavioral of top is
     signal dac_data_o : std_logic_vector(9 downto 0);
 
     signal host_clk_i : std_logic;
-    signal host_clk_o : std_logic;
 
     type transfer_direction is (from_adc, to_dac);
     signal transfer_direction_i : transfer_direction;
@@ -90,7 +88,6 @@ begin
                                 else (others => 'Z');
     data_from_host_i <= HOST_DATA;
 
-    HOST_CLK <= host_clk_o;
     HOST_CAPTURE <= host_data_capture_o;
     host_data_enable_i <= not HOST_DISABLE;
     transfer_direction_i <= to_dac when HOST_DIRECTION = '1'
@@ -98,10 +95,6 @@ begin
 
     ------------------------------------------------
     
-    host_clk_o <= host_clk_i;
-
-    ------------------------------------------------
-    
     process(host_clk_i)
     begin
         if rising_edge(host_clk_i) then
diff --git a/hardware/jellybean/sgpio_if/top_tb.vhd b/hardware/jellybean/sgpio_if/top_tb.vhd
index abd9dd92..3c15e9b2 100755
--- a/hardware/jellybean/sgpio_if/top_tb.vhd
+++ b/hardware/jellybean/sgpio_if/top_tb.vhd
@@ -29,7 +29,6 @@ ARCHITECTURE behavior OF top_tb IS
     COMPONENT top
     PORT(
         HOST_DATA : INOUT  std_logic_vector(7 downto 0);
-        HOST_CLK : OUT std_logic;
         HOST_CAPTURE : OUT std_logic;
         HOST_DISABLE : IN std_logic;
         HOST_DIRECTION : IN std_logic;
@@ -56,14 +55,12 @@ ARCHITECTURE behavior OF top_tb IS
 
  	--Outputs
     signal DD : std_logic_vector(9 downto 0);
-    signal HOST_CLK : std_logic;
     signal HOST_CAPTURE : std_logic;
     
 begin
  
     uut: top PORT MAP (
         HOST_DATA => HOST_DATA,
-        HOST_CLK => HOST_CLK,
         HOST_CAPTURE => HOST_CAPTURE,
         HOST_DISABLE => HOST_DISABLE,
         HOST_DIRECTION => HOST_DIRECTION,
@@ -126,10 +123,10 @@ begin
         
         for i in 0 to 10 loop
             HOST_DATA <= (others => '0');
-            wait until rising_edge(host_clk) and HOST_CAPTURE = '1';
+            wait until rising_edge(CODEC_CLK) and HOST_CAPTURE = '1';
             
             HOST_DATA <= (others => '1');
-            wait until rising_edge(host_clk) and HOST_CAPTURE = '1';
+            wait until rising_edge(CODEC_CLK) and HOST_CAPTURE = '1';
         end loop;
         
         wait;