Fixed indentation
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@ -30,8 +30,8 @@ entity top is
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Port(
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HOST_DATA : inout std_logic_vector(7 downto 0);
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HOST_CAPTURE : out std_logic;
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HOST_SYNC_CMD : out std_logic;
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HOST_SYNC : in std_logic;
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HOST_SYNC_CMD : out std_logic;
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HOST_SYNC : in std_logic;
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HOST_DISABLE : in std_logic;
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HOST_DIRECTION : in std_logic;
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HOST_DECIM_SEL : in std_logic_vector(2 downto 0);
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@ -58,9 +58,9 @@ architecture Behavioral of top is
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signal host_data_enable_i : std_logic;
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signal host_data_capture_o : std_logic;
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signal host_sync_o : std_logic := '0';
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signal host_sync_i : std_logic := '0';
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signal host_sync_latched : std_logic := '0';
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signal host_sync_o : std_logic := '0';
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signal host_sync_i : std_logic := '0';
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signal host_sync_latched : std_logic := '0';
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signal data_from_host_i : std_logic_vector(7 downto 0);
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signal data_to_host_o : std_logic_vector(7 downto 0);
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@ -158,17 +158,17 @@ begin
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end if;
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end process;
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process (host_data_enable_i, host_sync_i)
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begin
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host_sync_o <= host_data_enable_i;
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if host_data_enable_i = '1' then
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if rising_edge(host_sync_i) then
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host_sync_latched <= host_sync_i;
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end if;
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else
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host_sync_latched <= '0';
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end if;
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end process;
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process (host_data_enable_i, host_sync_i)
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begin
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host_sync_o <= host_data_enable_i;
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if host_data_enable_i = '1' then
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if rising_edge(host_sync_i) then
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host_sync_latched <= host_sync_i;
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end if;
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else
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host_sync_latched <= '0';
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end if;
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end process;
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process(host_clk_i)
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begin
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@ -178,9 +178,9 @@ begin
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host_data_capture_o <= host_data_enable_i and host_sync_latched;
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end if;
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else
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if codec_clk_i = '0' then
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host_data_capture_o <= host_data_enable_i and decimate_en and host_sync_latched;
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end if;
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if codec_clk_i = '0' then
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host_data_capture_o <= host_data_enable_i and decimate_en and host_sync_latched;
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end if;
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end if;
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end if;
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end process;
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