From d46a59fba3b4f5f38c5c35b4c0f99e387f7032ff Mon Sep 17 00:00:00 2001 From: TitanMKD Date: Mon, 26 Nov 2012 23:41:13 +0100 Subject: [PATCH] Fix for LPC4330 MCU frequency to be set to 204MHz instead of 102MHz. --- firmware/common/hackrf_core.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/firmware/common/hackrf_core.c b/firmware/common/hackrf_core.c index c6efb1dc..5f312bee 100644 --- a/firmware/common/hackrf_core.c +++ b/firmware/common/hackrf_core.c @@ -231,7 +231,7 @@ void cpu_clock_init(void) | CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_XTAL); /* use XTAL_OSC as clock source for PLL1 */ - /* Start PLL1 at 12MHz * 17 / 2 = 102MHz. */ + /* Start PLL1 at 12MHz * 17 / (2+2) = 51MHz. */ CGU_PLL1_CTRL = CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL) | CGU_PLL1_CTRL_PSEL(1) | CGU_PLL1_CTRL_NSEL(0) @@ -249,7 +249,8 @@ void cpu_clock_init(void) CGU_PLL1_CTRL = CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL) | CGU_PLL1_CTRL_PSEL(0) | CGU_PLL1_CTRL_NSEL(0) - | CGU_PLL1_CTRL_MSEL(16); + | CGU_PLL1_CTRL_MSEL(16) + | CGU_PLL1_CTRL_FBSEL; /* wait until stable */ while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK));