From d103c31187ec2c4dd421f7fa16493a5fa7140dfd Mon Sep 17 00:00:00 2001 From: Jared Boone Date: Fri, 18 Jan 2019 16:09:14 -0800 Subject: [PATCH] CPLD: Rework timing between ADC, CPLD, SGPIO Capture ADC and codec clock state with sufficient timing margin. Increase drive strength on codec clock and invert CPLD capture clock to provide margin for capturing codec clock (I vs. Q channel). --- firmware/common/sgpio.c | 2 +- firmware/common/si5351c.c | 4 ++-- firmware/cpld/sgpio_if/top.vhd | 17 ++++++++++++----- 3 files changed, 15 insertions(+), 8 deletions(-) diff --git a/firmware/common/sgpio.c b/firmware/common/sgpio.c index c128a74e..04303b87 100644 --- a/firmware/common/sgpio.c +++ b/firmware/common/sgpio.c @@ -157,7 +157,7 @@ void sgpio_configure( const uint_fast8_t pos = config->slice_mode_multislice ? 0x1f : 0x03; const bool single_slice = !config->slice_mode_multislice; const uint_fast8_t slice_count = config->slice_mode_multislice ? 8 : 1; - const uint_fast8_t clk_capture_mode = (direction == SGPIO_DIRECTION_TX) ? 0 : 1; + const uint_fast8_t clk_capture_mode = (direction == SGPIO_DIRECTION_TX) ? 0 : 0; uint32_t slice_enable_mask = 0; /* Configure Slice A, I, E, J, C, K, F, L (sgpio_slice_mode_multislice mode) */ diff --git a/firmware/common/si5351c.c b/firmware/common/si5351c.c index a217d6d5..64a3dda1 100644 --- a/firmware/common/si5351c.c +++ b/firmware/common/si5351c.c @@ -185,8 +185,8 @@ void si5351c_configure_clock_control(si5351c_driver_t* const drv, const enum pll /* Clock to CPU is deactivated as it is not used and creates noise */ /* External clock output is deactivated as it is not used and creates noise */ uint8_t data[] = {16 - ,SI5351C_CLK_FRAC_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA) - ,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA) + ,SI5351C_CLK_FRAC_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA) + ,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA) | SI5351C_CLK_INV ,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA) ,SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/ ,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_6MA) | SI5351C_CLK_INV diff --git a/firmware/cpld/sgpio_if/top.vhd b/firmware/cpld/sgpio_if/top.vhd index f65dadbd..87bdcc0f 100755 --- a/firmware/cpld/sgpio_if/top.vhd +++ b/firmware/cpld/sgpio_if/top.vhd @@ -75,14 +75,11 @@ begin ------------------------------------------------ -- Codec interface - adc_data_i <= DA(7 downto 0); DD(9 downto 0) <= dac_data_o; ------------------------------------------------ -- Clocks - codec_clk_i <= CODEC_CLK; - BUFG_host : BUFG port map ( O => host_clk_i, @@ -110,7 +107,17 @@ begin q_invert <= HOST_Q_INVERT; rx_q_invert_mask <= X"80" when q_invert = '1' else X"7f"; tx_q_invert_mask <= X"7F" when q_invert = '1' else X"80"; - + + process(host_clk_i) + begin + if rising_edge(host_clk_i) then + codec_clk_i <= CODEC_CLK; + if (transfer_direction_i = from_adc) then + adc_data_i <= DA(7 downto 0); + end if; + end if; + end process; + process(host_clk_i) begin if rising_edge(host_clk_i) then @@ -159,7 +166,7 @@ begin host_data_capture_o <= host_data_enable_i and (host_sync_latched or not host_sync_enable); end if; else - if codec_clk_i = '0' then + if codec_clk_i = '1' then host_data_capture_o <= host_data_enable_i and (host_sync_latched or not host_sync_enable); end if; end if;