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Fix clock edge for TX mode. TX data was completely crapped up due to skew on my Jellybean/Lemondrop board. Hopefully, this also applies to Jawbreaker. I'll recheck once I have hardware in-hand.

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This commit is contained in:
Jared Boone
2012-11-02 22:34:43 -07:00
parent f60383c161
commit cc5f1c61c7
1 changed files with 2 additions and 1 deletions
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3
firmware/common/sgpio.c
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@ -167,6 +167,7 @@ void sgpio_configure(
const bool input_slice = (i == 0) && (transceiver_mode == TRANSCEIVER_MODE_RX); const bool input_slice = (i == 0) && (transceiver_mode == TRANSCEIVER_MODE_RX);
const uint_fast8_t concat_order = (input_slice || single_slice) ? 0 : 3; const uint_fast8_t concat_order = (input_slice || single_slice) ? 0 : 3;
const uint_fast8_t concat_enable = (input_slice || single_slice) ? 0 : 1; const uint_fast8_t concat_enable = (input_slice || single_slice) ? 0 : 1;
const uint_fast8_t clk_capture_mode = (transceiver_mode == TRANSCEIVER_MODE_RX) ? 1 : 0;
SGPIO_MUX_CFG(slice_index) = SGPIO_MUX_CFG(slice_index) =
SGPIO_MUX_CFG_CONCAT_ORDER(concat_order) SGPIO_MUX_CFG_CONCAT_ORDER(concat_order)
@ -185,7 +186,7 @@ void sgpio_configure(
| SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE(0) | SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE(0)
| SGPIO_SLICE_MUX_CFG_INV_OUT_CLK(0) | SGPIO_SLICE_MUX_CFG_INV_OUT_CLK(0)
| SGPIO_SLICE_MUX_CFG_CLKGEN_MODE(1) | SGPIO_SLICE_MUX_CFG_CLKGEN_MODE(1)
| SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE(1) | SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE(clk_capture_mode)
| SGPIO_SLICE_MUX_CFG_MATCH_MODE(0) | SGPIO_SLICE_MUX_CFG_MATCH_MODE(0)
; ;