Adjustments for new auto-generated #defines.
This commit is contained in:
Jared Boone
@ -15,159 +15,16 @@
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#define ATTR_ALIGNED(x) __attribute__ ((aligned(x)))
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#define __DATA(x) __attribute__ ((section("x")))
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/*
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#define REGISTER_START(register_name) \
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#define REGISTER_FIELD_NAME(x) register_name##_x \
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typedef enum {
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#define REGISTER_BIT(name, ordinal) \
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REGISTER_FIELD_NAME(name##_bit) = ordinal, \
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REGISTER_FIELD_NAME(name) = (1 << ordinal),
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#define REGISTER_END(x) \
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} register_name_bit_t; \
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#undef REGISTER_NAME
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*/
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typedef enum {
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RESET_CTRL0_USB0_RST_bit = 17,
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} RESET_CTRL0_bit_t;
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//REGISTER_START(RESET_CTRL0)
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// REGISTER_BIT(USB0_RST, 17)
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//REGISTER_END(RESET_CTRL0)
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typedef enum {
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CREG_CREG0_USB0PHY_bit = 5,
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} CREG_CREG0_bit_t;
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typedef enum {
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USB0_USBCMD_D_RS_bit = 0,
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USB0_USBCMD_D_RS = 1 << USB0_USBCMD_D_RS_bit,
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USB0_USBCMD_D_RST_bit = 1,
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USB0_USBCMD_D_RST = 1 << USB0_USBCMD_D_RST_bit,
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USB0_USBCMD_D_ITC_base = 16,
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USB0_USBCMD_D_ITC_width = 8,
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USB0_USBCMD_D_ITC_mask = ((1 << USB0_USBCMD_D_ITC_width) - 1) <<
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USB0_USBCMD_D_ITC_base,
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} USB0_USBCMD_D_bit_t;
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typedef enum {
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USB0_USBSTS_UI_bit = 0,
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USB0_USBSTS_UI = 1 << USB0_USBSTS_UI_bit,
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USB0_USBSTS_UEI_bit = 1,
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USB0_USBSTS_UEI = 1 << USB0_USBSTS_UEI_bit,
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USB0_USBSTS_PCI_bit = 2,
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USB0_USBSTS_PCI = 1 << USB0_USBSTS_PCI_bit,
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USB0_USBSTS_AAI_bit = 5,
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USB0_USBSTS_AAI = 1 << USB0_USBSTS_AAI_bit,
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USB0_USBSTS_URI_bit = 6,
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USB0_USBSTS_URI = 1 << USB0_USBSTS_URI_bit,
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USB0_USBSTS_SRI_bit = 7,
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USB0_USBSTS_SRI = 1 << USB0_USBSTS_SRI_bit,
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USB0_USBSTS_SLI_bit = 8,
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USB0_USBSTS_SLI = 1 << USB0_USBSTS_SLI_bit,
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USB0_USBSTS_NAKI_bit = 16,
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USB0_USBSTS_NAKI = 1 << USB0_USBSTS_NAKI_bit,
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} USB0_USBSTS_bit_t;
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typedef enum {
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USB0_USBINTR_D_UE_bit = 0,
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USB0_USBINTR_D_UE = 1 << USB0_USBINTR_D_UE_bit,
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USB0_USBINTR_D_UEE_bit = 1,
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USB0_USBINTR_D_UEE = 1 << USB0_USBINTR_D_UEE_bit,
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USB0_USBINTR_D_PCE_bit = 2,
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USB0_USBINTR_D_PCE = 1 << USB0_USBINTR_D_PCE_bit,
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USB0_USBINTR_D_URE_bit = 6,
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USB0_USBINTR_D_URE = 1 << USB0_USBINTR_D_URE_bit,
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USB0_USBINTR_D_SRE_bit = 7,
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USB0_USBINTR_D_SRE = 1 << USB0_USBINTR_D_SRE_bit,
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USB0_USBINTR_D_SLE_bit = 8,
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USB0_USBINTR_D_SLE = 1 << USB0_USBINTR_D_SLE_bit,
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USB0_USBINTR_D_NAKE_bit = 16,
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USB0_USBINTR_D_NAKE = 1 << USB0_USBINTR_D_NAKE_bit,
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} USB0_USBINTR_D_bit_t;
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typedef enum {
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USB0_USBMODE_D_CM_base = 0,
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USB0_USBMODE_D_SLOM_bit = 3,
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USB0_USBMODE_D_SLOM = 1 << USB0_USBMODE_D_SLOM_bit,
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} USB0_USBMODE_D_bit_t;
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typedef enum {
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USB0_ENDPTCTRL0_RXS_bit = 0,
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USB0_ENDPTCTRL0_RXS = 1 << USB0_ENDPTCTRL0_RXS_bit,
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USB0_ENDPTCTRL0_RXT_base = 2,
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USB0_ENDPTCTRL0_RXE_bit = 7,
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USB0_ENDPTCTRL0_RXE = 1 << USB0_ENDPTCTRL0_RXE_bit,
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USB0_ENDPTCTRL0_TXS_bit = 16,
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USB0_ENDPTCTRL0_TXS = 1 << USB0_ENDPTCTRL0_TXS_bit,
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USB0_ENDPTCTRL0_TXT_base = 18,
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USB0_ENDPTCTRL0_TXT_width = 2,
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USB0_ENDPTCTRL0_TXT_mask = ((1 << USB0_ENDPTCTRL0_TXT_width) - 1) <<
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USB0_ENDPTCTRL0_TXT_base,
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USB0_ENDPTCTRL0_TXE_bit = 23,
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USB0_ENDPTCTRL0_TXE = 1 << USB0_ENDPTCTRL0_TXE_bit,
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} USB0_ENDPTCTRL0_bit_t;
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typedef enum {
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USB0_ENDPTCTRL_RXS_bit = 0,
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USB0_ENDPTCTRL_RXS = 1 << USB0_ENDPTCTRL_RXS_bit,
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USB0_ENDPTCTRL_RXT_base = 2,
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USB0_ENDPTCTRL_RXT_width = 2,
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USB0_ENDPTCTRL_RXT_mask = ((1 << USB0_ENDPTCTRL_RXT_width) - 1) <<
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USB0_ENDPTCTRL_RXT_base,
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USB0_ENDPTCTRL_RXI_bit = 5,
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USB0_ENDPTCTRL_RXI = 1 << USB0_ENDPTCTRL_RXI_bit,
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USB0_ENDPTCTRL_RXR_bit = 6,
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USB0_ENDPTCTRL_RXR = 1 << USB0_ENDPTCTRL_RXR_bit,
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USB0_ENDPTCTRL_RXE_bit = 7,
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USB0_ENDPTCTRL_RXE = 1 << USB0_ENDPTCTRL_RXE_bit,
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USB0_ENDPTCTRL_TXS_bit = 16,
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USB0_ENDPTCTRL_TXS = 1 << USB0_ENDPTCTRL_TXS_bit,
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USB0_ENDPTCTRL_TXT_base = 18,
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USB0_ENDPTCTRL_TXT_width = 2,
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USB0_ENDPTCTRL_TXT_mask = ((1 << USB0_ENDPTCTRL_TXT_width) - 1) <<
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USB0_ENDPTCTRL_TXT_base,
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USB0_ENDPTCTRL_TXE_bit = 23,
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USB0_ENDPTCTRL_TXE = 1 << USB0_ENDPTCTRL_TXE_bit,
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} USB0_ENDPTCTRL_bit_t;
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void usb_reset_peripheral() {
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RESET_CTRL0 = (1 << RESET_CTRL0_USB0_RST_bit);
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RESET_CTRL0 = RESET_CTRL0_USB0_RST;
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RESET_CTRL0 = 0;
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while( (RESET_ACTIVE_STATUS0 & (1 << RESET_CTRL0_USB0_RST_bit)) == 0 );
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while( (RESET_ACTIVE_STATUS0 & RESET_CTRL0_USB0_RST) == 0 );
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}
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void usb_enable_phy() {
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peripheral_bitband_clear(&CREG_CREG0, CREG_CREG0_USB0PHY_bit);
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peripheral_bitband_clear(&CREG_CREG0, CREG_CREG0_USB0PHY_SHIFT);
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}
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void usb_wait_for_endpoint_priming_to_finish() {
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@ -185,11 +42,11 @@ void usb_flush_all_primed_endpoints() {
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}
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void usb_stop_controller() {
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peripheral_bitband_clear(&USB0_USBCMD_D, USB0_USBCMD_D_RS_bit);
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peripheral_bitband_clear(&USB0_USBCMD_D, USB0_USBCMD_D_RS_SHIFT);
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}
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void usb_run_controller() {
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peripheral_bitband_set(&USB0_USBCMD_D, USB0_USBCMD_D_RS_bit);
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peripheral_bitband_set(&USB0_USBCMD_D, USB0_USBCMD_D_RS_SHIFT);
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}
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uint_fast8_t usb_controller_is_resetting() {
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@ -279,13 +136,13 @@ void usb_init() {
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usb_enable_phy();
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usb_reset_controller();
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USB0_USBMODE_D =
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(1 << USB0_USBMODE_D_SLOM_bit) |
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(2 << USB0_USBMODE_D_CM_base);
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USB0_USBMODE_D_SLOM |
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USB0_USBMODE_D_CM1_0(2);
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nvic_enable_irq(NVIC_M4_USB0_IRQ);
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// Set interrupt threshold interval to 0
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USB0_USBCMD_D &= ~(USB0_USBCMD_D_ITC_mask);
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USB0_USBCMD_D &= ~(USB0_USBCMD_D_ITC_MASK);
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USB0_ENDPOINTLISTADDR = (uint32_t)&queue_head;
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for(uint_fast8_t i=0; i<2; i++) {
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@ -319,11 +176,11 @@ int main(void) {
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enable_1v8_power();
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cpu_clock_init();
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CGU_BASE_PERIPH_CLK = (CGU_BASE_CLK_AUTOBLOCK
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| (CGU_SRC_PLL1 << CGU_BASE_CLK_SEL_SHIFT));
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CGU_BASE_PERIPH_CLK = CGU_BASE_PERIPH_CLK_AUTOBLOCK
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| CGU_BASE_PERIPH_CLK_CLK_SEL(CGU_SRC_PLL1);
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CGU_BASE_APB1_CLK = (CGU_BASE_CLK_AUTOBLOCK
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| (CGU_SRC_PLL1 << CGU_BASE_CLK_SEL_SHIFT));
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CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK
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| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_PLL1);
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usb_reset_peripheral();
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