From cb15d4a83a9abb9709cfc4204cc7554f96fb58bc Mon Sep 17 00:00:00 2001 From: Michael Ossmann Date: Tue, 1 May 2012 09:08:26 -0600 Subject: [PATCH] set PLLs to integer-only mode --- hardware/test/si5351-configure.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hardware/test/si5351-configure.py b/hardware/test/si5351-configure.py index c7d667c1..eeb4c4bd 100644 --- a/hardware/test/si5351-configure.py +++ b/hardware/test/si5351-configure.py @@ -113,7 +113,7 @@ write_registers(3, 0xFF) write_registers(9, 0xFF) # Power down all CLKx -write_registers(16, (0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80)) +write_registers(16, (0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0xC0, 0xC0)) # Register 183: Crystal Internal Load Capacitance # Reads as 0xE4 on power-up @@ -175,7 +175,7 @@ write_registers(92, 0x00) # CLK4_INV=0 (not inverted) # CLK4_SRC=3 (MS4 as input source) # CLK4_IDRV=3 (8mA) -write_registers(16, (0x4F, 0x4F, 0x80, 0x80, 0x0F, 0x80, 0x80, 0x80)) +write_registers(16, (0x4F, 0x4F, 0x80, 0x80, 0x0F, 0x80, 0xC0, 0xC0)) # Enable CLK outputs 0, 1, 4 only. write_registers(3, 0xFF ^ 0b00010011)