Moved CGU peripheral and APB1 base clock configurations to before SSP1 configuration.
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@ -314,6 +314,13 @@ int main(void) {
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pin_setup();
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pin_setup();
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enable_1v8_power();
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enable_1v8_power();
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cpu_clock_init();
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cpu_clock_init();
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CGU_BASE_PERIPH_CLK = (CGU_BASE_CLK_AUTOBLOCK
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| (CGU_SRC_PLL1 << CGU_BASE_CLK_SEL_SHIFT));
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CGU_BASE_APB1_CLK = (CGU_BASE_CLK_AUTOBLOCK
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| (CGU_SRC_PLL1 << CGU_BASE_CLK_SEL_SHIFT));
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ssp1_init();
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ssp1_init();
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ssp1_set_mode_max2837();
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ssp1_set_mode_max2837();
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@ -322,12 +329,6 @@ int main(void) {
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max2837_start();
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max2837_start();
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max2837_rx();
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max2837_rx();
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CGU_BASE_PERIPH_CLK = (CGU_BASE_CLK_AUTOBLOCK
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| (CGU_SRC_PLL1 << CGU_BASE_CLK_SEL_SHIFT));
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CGU_BASE_APB1_CLK = (CGU_BASE_CLK_AUTOBLOCK
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| (CGU_SRC_PLL1 << CGU_BASE_CLK_SEL_SHIFT));
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ssp1_set_mode_max5864();
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ssp1_set_mode_max5864();
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max5864_xcvr();
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max5864_xcvr();
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configure_sgpio_test_rx();
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configure_sgpio_test_rx();
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