chore(rad1o): White space fixes and cleanup

Makefile

@@ -27,7 +27,7 @@ $(FDIR)/hackrf_usb.dfu: $(FDIR) $(FDIR)/Makefile $(FORCE)
 
 $(FDIR)/Makefile:
 	cd $(FDIR) && cmake -DBOARD=RAD1O ..
-	
+
 $(FDIR):
 	mkdir $(FDIR)
 

firmware/common/hackrf_core.c

@@ -625,8 +625,7 @@ void cpu_clock_init(void)
 #endif
 
 #ifdef RAD1O
-	/*
+	/* rad1o clocks:
-	 * rad1o clocks:
 	 *   CLK0 -> MAX5864/CPLD
 	 *   CLK1 -> CPLD
 	 *   CLK2 -> SGPIO
@@ -634,8 +633,7 @@ void cpu_clock_init(void)
 	 *   CLK4 -> MAX2837
 	 *   CLK5 -> MAX2871
 	 *   CLK6 -> none
-	 *   CLK7 -> LPC4330 (but LPC4330 starts up on its own crystal)
+	 *   CLK7 -> LPC4330 (but LPC4330 starts up on its own crystal) */
-	 */
 
 	/* MS3/CLK3 is the source for the external clock output. */
 	si5351c_configure_multisynth(&clock_gen, 3, 80*128-512, 0, 1, 0); /* 800/80 = 10MHz */
@@ -655,7 +653,6 @@ void cpu_clock_init(void)
 
 	/* Set to 10 MHz, the common rate between Jellybean and Jawbreaker. */
 	sample_rate_set(10000000);
-	//sample_rate_set(8000000);
 
 	si5351c_set_clock_source(&clock_gen, PLL_SOURCE_XTAL);
 	// soft reset

firmware/common/hackrf_core.h

@@ -143,9 +143,9 @@ extern "C"
 #define SCU_XCVR_B7			(P5_6)	/* GPIO2[15] on P5_6 */
 #endif
 #ifdef RAD1O
-#define SCU_XCVR_RXHP		(P8_1)	/* GPIO[] on P8_1 */
+#define SCU_XCVR_RXHP       (P8_1)  /* GPIO[] on P8_1 */
-#define SCU_XCVR_B6			(P8_2)	/* GPIO[] on P8_2 */
+#define SCU_XCVR_B6         (P8_2)  /* GPIO[] on P8_2 */
-#define SCU_XCVR_B7			(P9_3)	/* GPIO[] on P8_3 */
+#define SCU_XCVR_B7         (P9_3)  /* GPIO[] on P8_3 */
 #endif
 
 #define SCU_XCVR_ENABLE     (P4_6)  /* GPIO2[6] on P4_6 */

firmware/common/max2871.c

@@ -23,11 +23,11 @@ void max2871_setup(max2871_driver_t* const drv)
 	/* Configure GPIO pins. */
 	scu_pinmux(SCU_VCO_CE, SCU_GPIO_FAST);
 	scu_pinmux(SCU_VCO_SCLK, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
-	//Only used for the debug pin config: scu_pinmux(SCU_VCO_SCLK, SCU_GPIO_FAST);
+	/* Only used for the debug pin config: scu_pinmux(SCU_VCO_SCLK, SCU_GPIO_FAST); */
 	scu_pinmux(SCU_VCO_SDATA, SCU_GPIO_FAST);
 	scu_pinmux(SCU_VCO_LE, SCU_GPIO_FAST);
 	scu_pinmux(SCU_VCO_MUX, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
-    scu_pinmux(SCU_SYNT_RFOUT_EN, SCU_GPIO_FAST);
+	scu_pinmux(SCU_SYNT_RFOUT_EN, SCU_GPIO_FAST);
 
 	/* Set GPIO pins as outputs. */
 	gpio_output(drv->gpio_vco_ce);
@@ -36,8 +36,8 @@ void max2871_setup(max2871_driver_t* const drv)
 	gpio_output(drv->gpio_vco_le);
 	gpio_output(drv->gpio_synt_rfout_en);
 
-    /* MUX is an input */
+	/* MUX is an input */
-    gpio_input(drv->gpio_vco_mux);
+	gpio_input(drv->gpio_vco_mux);
 
 	/* set to known state */
 	gpio_set(drv->gpio_vco_ce); /* active high */
@@ -46,73 +46,73 @@ void max2871_setup(max2871_driver_t* const drv)
 	gpio_set(drv->gpio_vco_le); /* active low */
 	gpio_set(drv->gpio_synt_rfout_en); /* active high */
 
-    max2871_regs_init();
+	max2871_regs_init();
-    int i;
+	int i;
-    for(i = 5; i >= 0; i--) {
+	for(i = 5; i >= 0; i--) {
-        max2871_spi_write(drv, i, max2871_get_register(i));
+		max2871_spi_write(drv, i, max2871_get_register(i));
-        delay_ms(20);
+		delay_ms(20);
-    }
+	}
 
-    max2871_set_INT(1);
+	max2871_set_INT(1);
-    max2871_set_N(4500);
+	max2871_set_N(4500);
-    max2871_set_FRAC(0);
+	max2871_set_FRAC(0);
-    max2871_set_CPL(0);
+	max2871_set_CPL(0);
-    max2871_set_CPT(0);
+	max2871_set_CPT(0);
-    max2871_set_P(1);
+	max2871_set_P(1);
-    max2871_set_M(0);
+	max2871_set_M(0);
-    max2871_set_LDS(0);
+	max2871_set_LDS(0);
-    max2871_set_SDN(0);
+	max2871_set_SDN(0);
-    max2871_set_MUX(0x0C);  // Register 6 readback
+	max2871_set_MUX(0x0C);  /* Register 6 readback */
-    max2871_set_DBR(0);
+	max2871_set_DBR(0);
-    max2871_set_RDIV2(0);
+	max2871_set_RDIV2(0);
-    max2871_set_R(1); // 40 MHz f_PFD
+	max2871_set_R(1); /* 40 MHz f_PFD */
-    max2871_set_REG4DB(1);
+	max2871_set_REG4DB(1);
-    max2871_set_CP(15); // ?: CP charge pump current 0-15
+	max2871_set_CP(15); /* ?: CP charge pump current 0-15 */
-    max2871_set_LDF(1); // INT-N
+	max2871_set_LDF(1); /* INT-N */
-    max2871_set_LDP(0); // ?: Lock-Detect Precision
+	max2871_set_LDP(0); /* ?: Lock-Detect Precision */
-    max2871_set_PDP(1);
+	max2871_set_PDP(1);
-    max2871_set_SHDN(0);
+	max2871_set_SHDN(0);
-    max2871_set_TRI(0);
+	max2871_set_TRI(0);
-    max2871_set_RST(0);
+	max2871_set_RST(0);
-    max2871_set_VCO(0);
+	max2871_set_VCO(0);
-    max2871_set_VAS_SHDN(0);
+	max2871_set_VAS_SHDN(0);
-    max2871_set_VAS_TEMP(1);
+	max2871_set_VAS_TEMP(1);
-    max2871_set_CSM(0);
+	max2871_set_CSM(0);
-    max2871_set_MUTEDEL(1);
+	max2871_set_MUTEDEL(1);
-    max2871_set_CDM(0);
+	max2871_set_CDM(0);
-    max2871_set_CDIV(0);
+	max2871_set_CDIV(0);
-    max2871_set_SDLDO(0);
+	max2871_set_SDLDO(0);
-    max2871_set_SDDIV(0);
+	max2871_set_SDDIV(0);
-    max2871_set_SDREF(0);
+	max2871_set_SDREF(0);
-    max2871_set_BS(20*40); // For 40 MHz f_PFD
+	max2871_set_BS(20*40); /* For 40 MHz f_PFD */
-    max2871_set_FB(1); // Do not put DIVA into the feedback loop
+	max2871_set_FB(1); /* Do not put DIVA into the feedback loop */
-    max2871_set_DIVA(0);
+	max2871_set_DIVA(0);
-    max2871_set_SDVCO(0);
+	max2871_set_SDVCO(0);
-    max2871_set_MTLD(1);
+	max2871_set_MTLD(1);
-    max2871_set_BDIV(0);
+	max2871_set_BDIV(0);
-    max2871_set_RFB_EN(0);
+	max2871_set_RFB_EN(0);
-    max2871_set_BPWR(0);
+	max2871_set_BPWR(0);
-    max2871_set_RFA_EN(0);
+	max2871_set_RFA_EN(0);
-    max2871_set_APWR(3);
+	max2871_set_APWR(3);
-    max2871_set_SDPLL(0);
+	max2871_set_SDPLL(0);
-    max2871_set_F01(1);
+	max2871_set_F01(1);
-    max2871_set_LD(1);
+	max2871_set_LD(1);
-    max2871_set_ADCS(0);
+	max2871_set_ADCS(0);
-    max2871_set_ADCM(0);
+	max2871_set_ADCM(0);
 
-    max2871_write_registers(drv);
+	max2871_write_registers(drv);
 
-    max2871_set_frequency(drv, 3500);
+	max2871_set_frequency(drv, 3500);
 }
 
 static void delay_ms(int ms)
 {
 	uint32_t i;
-    while(ms--) {
+	while(ms--) {
-        for (i = 0; i < 20000; i++) {
+		for (i = 0; i < 20000; i++) {
-            __asm__("nop");
+			__asm__("nop");
-        }
+		}
-    }
+	}
 }
 
 
@@ -129,8 +129,7 @@ static void serial_delay(void)
  *
  * Send 32 bits:
  *  First 29 bits are data
- *  Last 3 bits are register number
+ *  Last 3 bits are register number */
- */
 static void max2871_spi_write(max2871_driver_t* const drv, uint8_t r, uint32_t v) {
 #if DEBUG
 	LOG("0x%04x -> reg%d\n", v, r);
@@ -171,13 +170,13 @@ static uint32_t max2871_spi_read(max2871_driver_t* const drv)
 	uint32_t bits = 32;
 	uint32_t data = 0;
 
-    max2871_spi_write(drv, 0x06, 0x0);
+	max2871_spi_write(drv, 0x06, 0x0);
 
-    serial_delay();
+	serial_delay();
-    gpio_set(drv->gpio_vco_sclk);
+	gpio_set(drv->gpio_vco_sclk);
-    serial_delay();
+	serial_delay();
-    gpio_clear(drv->gpio_vco_sclk);
+	gpio_clear(drv->gpio_vco_sclk);
-    serial_delay();
+	serial_delay();
 
 	while (bits--) {
 		gpio_set(drv->gpio_vco_sclk);
@@ -187,43 +186,43 @@ static uint32_t max2871_spi_read(max2871_driver_t* const drv)
 		serial_delay();
 
 		data <<= 1;
-        data |= gpio_read(drv->gpio_vco_mux) ? 1 : 0;
+		data |= gpio_read(drv->gpio_vco_mux) ? 1 : 0;
 	}
-    return data;
+	return data;
 }
 
 static void max2871_write_registers(max2871_driver_t* const drv)
 {
-    int i;
+	int i;
-    for(i = 5; i >= 0; i--) {
+	for(i = 5; i >= 0; i--) {
-        max2871_spi_write(drv, i, max2871_get_register(i));
+		max2871_spi_write(drv, i, max2871_get_register(i));
-    }
+	}
 }
 
 /* Set frequency (MHz). */
 uint64_t max2871_set_frequency(max2871_driver_t* const drv, uint16_t mhz)
 {
-    int n = mhz / 40;
+	int n = mhz / 40;
-    int diva = 0;
+	int diva = 0;
 
-    while(n * 40 < 3000) {
+	while(n * 40 < 3000) {
-        n *= 2;
+		n *= 2;
-        diva += 1;
+		diva += 1;
-    }
+	}
 
-    max2871_set_RFA_EN(0);
+	max2871_set_RFA_EN(0);
-    max2871_write_registers(drv);
+	max2871_write_registers(drv);
 
-    max2871_set_N(n);
+	max2871_set_N(n);
-    max2871_set_DIVA(diva);
+	max2871_set_DIVA(diva);
-    max2871_write_registers(drv);
+	max2871_write_registers(drv);
 
-    while(max2871_spi_read(drv) & MAX2871_VASA);
+	while(max2871_spi_read(drv) & MAX2871_VASA);
 
-    max2871_set_RFA_EN(1);
+	max2871_set_RFA_EN(1);
-    max2871_write_registers(drv);
+	max2871_write_registers(drv);
 
-    return (mhz/40)*40 * 1000000;
+	return (mhz/40)*40 * 1000000;
 }
 
 void max2871_enable(max2871_driver_t* const drv)

firmware/common/rf_path.c

@@ -221,10 +221,6 @@ static void switchctrl_set_rad1o(rf_path_t* const rf_path, uint8_t ctrl) {
 	if (ctrl & SWITCHCTRL_NO_RX_AMP_PWR) {
 		gpio_clear(rf_path->gpio_rx_lna);
 	}
-
-	if (ctrl & SWITCHCTRL_ANT_PWR) {
-		// TODO
-	}
 }
 #endif
 

firmware/common/sgpio.c

@@ -93,8 +93,8 @@ void sgpio_configure(
 		;
 
 #ifdef RAD1O
-	// The data direction might have changed. Check if we need to
+	/* The data direction might have changed. Check if we need to
-	// adjust the q inversion.
+	 * adjust the q inversion. */
 	update_q_invert(config);
 #endif
 
@@ -283,19 +283,16 @@ bool sgpio_cpld_stream_rx_set_decimation(sgpio_config_t* const config, const uin
  * have to go.
  *
  * As TX/RX can change without sgpio_cpld_stream_rx_set_q_invert
- * being called, we store a local copy of its parameter.
+ * being called, we store a local copy of its parameter. */
- */
 static bool sgpio_invert = false;
 
-/*
+/* Called when TX/RX changes od sgpio_cpld_stream_rx_set_q_invert
- * Called when TX/RX changes od sgpio_cpld_stream_rx_set_q_invert
+ * gets called. */
- * gets called.
- */
 static void update_q_invert(sgpio_config_t* const config) {
-	/* 1=Output SGPIO11 High(TX mode), 0=Output SGPIO11 Low(RX mode)*/
+	/* 1=Output SGPIO11 High(TX mode), 0=Output SGPIO11 Low(RX mode) */
 	bool tx_mode = (SGPIO_GPIO_OUTREG & (1 << 11)) > 0;
 
-	// 0.13: P1_18
+	/* 0.13: P1_18 */
 	if( !sgpio_invert & !tx_mode) {
 		gpio_write(config->gpio_rx_q_invert, 1);
 	} else if( !sgpio_invert & tx_mode) {

firmware/common/si5351c.c

@@ -271,12 +271,12 @@ void si5351c_configure_clock_control(si5351c_driver_t* const drv, const enum pll
  void si5351c_enable_clock_outputs(si5351c_driver_t* const drv)
  {
 #ifdef RAD1O
-    /* Enable CLK outputs 0, 1, 2, 4, 5 only. */
+	/* Enable CLK outputs 0, 1, 2, 4, 5 only. */
 	/* 7: Clock to CPU is deactivated as it is not used and creates noise */
 	/* 3: External clock output is deactivated as it is not used and creates noise */
-    uint8_t data[] = { 3, ~((1 << 0) | (1 << 1) | (1 << 2) | (1 << 4) | (1 << 5))};
+	uint8_t data[] = { 3, ~((1 << 0) | (1 << 1) | (1 << 2) | (1 << 4) | (1 << 5))};
 #else
-    /* Enable CLK outputs 0, 1, 2, 3, 4, 5, 7 only. */
+	/* Enable CLK outputs 0, 1, 2, 3, 4, 5, 7 only. */
 	uint8_t data[] = { 3, 0x40 };
 #endif
  	si5351c_write(drv, data, sizeof(data));

firmware/hackrf_usb/hackrf_usb.c

@@ -58,8 +58,8 @@ static const usb_request_handler_fn vendor_request_handler[] = {
 	usb_vendor_request_set_sample_rate_frac,
 	usb_vendor_request_set_baseband_filter_bandwidth,
 #ifdef RAD1O
-    NULL,
+	NULL, // write_rffc5071 not used
-    NULL,
+	NULL, // read_rffc5071 not used
 #else
 	usb_vendor_request_write_rffc5071,
 	usb_vendor_request_read_rffc5071,
@@ -163,6 +163,8 @@ int main(void) {
 	enable_1v8_power();
 #if (defined HACKRF_ONE || defined RAD1O)
 	enable_rf_power();
+
+	/* Let the voltage stabilize */
 	delay(1000000);
 #endif
 	cpu_clock_init();