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Move buffer allocation to before enabling CPLD I/O, so as not to mess up I/Q synchronization.

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This commit is contained in:
Jared Boone
2012-06-15 16:16:05 -07:00
parent e32a60495a
commit bab6ec5fef
1 changed files with 3 additions and 2 deletions
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5
firmware/sgpio/sgpio.c
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@ -254,11 +254,12 @@ void configure_sgpio_test_rx() {
SGPIO_REG(SGPIO_SLICE_A) = 0xCAFEBABE; // Primary output data register SGPIO_REG(SGPIO_SLICE_A) = 0xCAFEBABE; // Primary output data register
SGPIO_REG_SS(SGPIO_SLICE_A) = 0xDEADBEEF; // Shadow output data register SGPIO_REG_SS(SGPIO_SLICE_A) = 0xDEADBEEF; // Shadow output data register
volatile uint32_t buffer[4096];
uint32_t i = 0;
// Enable codec data stream. // Enable codec data stream.
SGPIO_GPIO_OUTREG &= ~(1L << 10); SGPIO_GPIO_OUTREG &= ~(1L << 10);
volatile uint32_t buffer[4096];
uint32_t i = 0;
while(true) { while(true) {
while(SGPIO_STATUS_1 == 0); while(SGPIO_STATUS_1 == 0);
SGPIO_CLR_STATUS_1 = 1; SGPIO_CLR_STATUS_1 = 1;