Use an empty block for empty while loops.

This commit is contained in:
Martin Ling
2022-06-27 12:15:36 +01:00
parent 414b4a98da
commit b4c828915a
11 changed files with 31 additions and 28 deletions

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@ -70,17 +70,17 @@ __attribute__((used)) void hard_fault_handler_c(uint32_t* args)
} }
} }
*/ */
while(1); while (1) {}
} }
void mem_manage_handler() { void mem_manage_handler() {
while(1); while (1) {}
} }
void bus_fault_handler() { void bus_fault_handler() {
while(1); while (1) {}
} }
void usage_fault_handler() { void usage_fault_handler() {
while(1); while (1) {}
} }

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@ -25,7 +25,7 @@
void gpdma_controller_enable() { void gpdma_controller_enable() {
GPDMA_CONFIG |= GPDMA_CONFIG_E(1); GPDMA_CONFIG |= GPDMA_CONFIG_E(1);
while( (GPDMA_CONFIG & GPDMA_CONFIG_E_MASK) == 0 ); while ((GPDMA_CONFIG & GPDMA_CONFIG_E_MASK) == 0) {}
} }
void gpdma_channel_enable(const uint_fast8_t channel) { void gpdma_channel_enable(const uint_fast8_t channel) {
@ -34,7 +34,7 @@ void gpdma_channel_enable(const uint_fast8_t channel) {
void gpdma_channel_disable(const uint_fast8_t channel) { void gpdma_channel_disable(const uint_fast8_t channel) {
GPDMA_CCONFIG(channel) &= ~GPDMA_CCONFIG_E_MASK; GPDMA_CCONFIG(channel) &= ~GPDMA_CCONFIG_E_MASK;
while( (GPDMA_ENBLDCHNS & GPDMA_ENBLDCHNS_ENABLEDCHANNELS(1 << channel)) ); while (GPDMA_ENBLDCHNS & GPDMA_ENBLDCHNS_ENABLEDCHANNELS(1 << channel)) {}
} }
void gpdma_channel_interrupt_tc_clear(const uint_fast8_t channel) { void gpdma_channel_interrupt_tc_clear(const uint_fast8_t channel) {

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@ -540,7 +540,7 @@ static void cpu_clock_pll1_max_speed(void)
CGU_PLL1_CTRL = reg_val; CGU_PLL1_CTRL = reg_val;
/* 6. Wait for PLL1 to lock. */ /* 6. Wait for PLL1 to lock. */
while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK_MASK)); while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK_MASK)) {}
/* 7. Set the PLL1 P-divider to divide by 2 (DIRECT=0, PSEL=0). */ /* 7. Set the PLL1 P-divider to divide by 2 (DIRECT=0, PSEL=0). */
CGU_PLL1_CTRL &= ~CGU_PLL1_CTRL_DIRECT_MASK; CGU_PLL1_CTRL &= ~CGU_PLL1_CTRL_DIRECT_MASK;
@ -635,7 +635,7 @@ void cpu_clock_init(void)
CGU_PLL0USB_CTRL = CGU_PLL0USB_CTRL_PD(1) CGU_PLL0USB_CTRL = CGU_PLL0USB_CTRL_PD(1)
| CGU_PLL0USB_CTRL_AUTOBLOCK(1) | CGU_PLL0USB_CTRL_AUTOBLOCK(1)
| CGU_PLL0USB_CTRL_CLK_SEL(CGU_SRC_XTAL); | CGU_PLL0USB_CTRL_CLK_SEL(CGU_SRC_XTAL);
while (CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK_MASK); while (CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK_MASK) {}
/* configure PLL0USB to produce 480 MHz clock from 12 MHz XTAL_OSC */ /* configure PLL0USB to produce 480 MHz clock from 12 MHz XTAL_OSC */
/* Values from User Manual v1.4 Table 94, for 12MHz oscillator. */ /* Values from User Manual v1.4 Table 94, for 12MHz oscillator. */
@ -648,7 +648,7 @@ void cpu_clock_init(void)
/* power on PLL0USB and wait until stable */ /* power on PLL0USB and wait until stable */
CGU_PLL0USB_CTRL &= ~CGU_PLL0USB_CTRL_PD_MASK; CGU_PLL0USB_CTRL &= ~CGU_PLL0USB_CTRL_PD_MASK;
while (!(CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK_MASK)); while (!(CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK_MASK)) {}
/* use PLL0USB as clock source for USB0 */ /* use PLL0USB as clock source for USB0 */
CGU_BASE_USB0_CLK = CGU_BASE_USB0_CLK_AUTOBLOCK(1) CGU_BASE_USB0_CLK = CGU_BASE_USB0_CLK_AUTOBLOCK(1)

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@ -217,7 +217,7 @@ uint64_t max2871_set_frequency(max2871_driver_t* const drv, uint16_t mhz)
max2871_set_DIVA(diva); max2871_set_DIVA(diva);
max2871_write_registers(drv); max2871_write_registers(drv);
while(max2871_spi_read(drv) & MAX2871_VASA); while(max2871_spi_read(drv) & MAX2871_VASA) {}
max2871_set_RFA_EN(1); max2871_set_RFA_EN(1);
max2871_write_registers(drv); max2871_write_registers(drv);

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@ -58,15 +58,15 @@ void spi_ssp_stop(spi_bus_t* const bus) {
} }
static void spi_ssp_wait_for_tx_fifo_not_full(spi_bus_t* const bus) { static void spi_ssp_wait_for_tx_fifo_not_full(spi_bus_t* const bus) {
while( (SSP_SR(bus->obj) & SSP_SR_TNF) == 0 ); while( (SSP_SR(bus->obj) & SSP_SR_TNF) == 0 ) {}
} }
static void spi_ssp_wait_for_rx_fifo_not_empty(spi_bus_t* const bus) { static void spi_ssp_wait_for_rx_fifo_not_empty(spi_bus_t* const bus) {
while( (SSP_SR(bus->obj) & SSP_SR_RNE) == 0 ); while( (SSP_SR(bus->obj) & SSP_SR_RNE) == 0 ) {}
} }
static void spi_ssp_wait_for_not_busy(spi_bus_t* const bus) { static void spi_ssp_wait_for_not_busy(spi_bus_t* const bus) {
while( SSP_SR(bus->obj) & SSP_SR_BSY ); while( SSP_SR(bus->obj) & SSP_SR_BSY ) {}
} }
static uint32_t spi_ssp_transfer_word(spi_bus_t* const bus, const uint32_t data) { static uint32_t spi_ssp_transfer_word(spi_bus_t* const bus, const uint32_t data) {

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@ -69,7 +69,7 @@ void usb_peripheral_reset() {
RESET_CTRL0 = RESET_CTRL0_USB0_RST; RESET_CTRL0 = RESET_CTRL0_USB0_RST;
RESET_CTRL0 = 0; RESET_CTRL0 = 0;
while( (RESET_ACTIVE_STATUS0 & RESET_CTRL0_USB0_RST) == 0 ); while( (RESET_ACTIVE_STATUS0 & RESET_CTRL0_USB0_RST) == 0 ) {}
} }
void usb_phy_enable() { void usb_phy_enable() {
@ -91,7 +91,7 @@ static void usb_clear_all_pending_interrupts() {
static void usb_wait_for_endpoint_priming_to_finish(const uint32_t mask) { static void usb_wait_for_endpoint_priming_to_finish(const uint32_t mask) {
// Wait until controller has parsed new transfer descriptors and prepared // Wait until controller has parsed new transfer descriptors and prepared
// receive buffers. // receive buffers.
while( USB0_ENDPTPRIME & mask ); while( USB0_ENDPTPRIME & mask ) {}
} }
static void usb_flush_endpoints(const uint32_t mask) { static void usb_flush_endpoints(const uint32_t mask) {
@ -103,7 +103,7 @@ static void usb_flush_endpoints(const uint32_t mask) {
static void usb_wait_for_endpoint_flushing_to_finish(const uint32_t mask) { static void usb_wait_for_endpoint_flushing_to_finish(const uint32_t mask) {
// Wait until controller has flushed all endpoints / cleared any primed // Wait until controller has flushed all endpoints / cleared any primed
// buffers. // buffers.
while( USB0_ENDPTFLUSH & mask ); while( USB0_ENDPTFLUSH & mask ) {}
} }
static void usb_flush_primed_endpoints(const uint32_t mask) { static void usb_flush_primed_endpoints(const uint32_t mask) {
@ -210,7 +210,7 @@ void usb_endpoint_schedule_wait(
// Ensure that endpoint is ready to be primed. // Ensure that endpoint is ready to be primed.
// It may have been flushed due to an aborted transaction. // It may have been flushed due to an aborted transaction.
// TODO: This should be preceded by a flush? // TODO: This should be preceded by a flush?
while( usb_endpoint_is_ready(endpoint) ); while( usb_endpoint_is_ready(endpoint) ) {}
td->next_dtd_pointer = USB_TD_NEXT_DTD_POINTER_TERMINATE; td->next_dtd_pointer = USB_TD_NEXT_DTD_POINTER_TERMINATE;
@ -437,7 +437,7 @@ static void usb_controller_reset() {
// all primed endpoints and stopping controller. // all primed endpoints and stopping controller.
USB0_USBCMD_D = USB0_USBCMD_D_RST; USB0_USBCMD_D = USB0_USBCMD_D_RST;
while( usb_controller_is_resetting() ); while( usb_controller_is_resetting() ) {}
} }
static void usb_bus_reset(usb_device_t* const device) { static void usb_bus_reset(usb_device_t* const device) {

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@ -39,7 +39,8 @@ static usb_queue_t* endpoint_queue(
const usb_endpoint_t* const endpoint const usb_endpoint_t* const endpoint
) { ) {
uint32_t index = USB_ENDPOINT_INDEX(endpoint->address); uint32_t index = USB_ENDPOINT_INDEX(endpoint->address);
if (endpoint_queues[index] == NULL) while (1); if (endpoint_queues[index] == NULL)
while (1) {}
return endpoint_queues[index]; return endpoint_queues[index];
} }
@ -47,7 +48,8 @@ void usb_queue_init(
usb_queue_t* const queue usb_queue_t* const queue
) { ) {
uint32_t index = USB_ENDPOINT_INDEX(queue->endpoint->address); uint32_t index = USB_ENDPOINT_INDEX(queue->endpoint->address);
if (endpoint_queues[index] != NULL) while (1); if (endpoint_queues[index] != NULL)
while (1) {}
endpoint_queues[index] = queue; endpoint_queues[index] = queue;
usb_transfer_t* t = queue->free_transfers; usb_transfer_t* t = queue->free_transfers;
@ -191,7 +193,8 @@ int usb_transfer_schedule_ack(
void usb_queue_transfer_complete(usb_endpoint_t* const endpoint) void usb_queue_transfer_complete(usb_endpoint_t* const endpoint)
{ {
usb_queue_t* const queue = endpoint_queue(endpoint); usb_queue_t* const queue = endpoint_queue(endpoint);
if (queue == NULL) while(1); // Uh oh if (queue == NULL)
while(1) {} // Uh oh
usb_transfer_t* transfer = queue->active; usb_transfer_t* transfer = queue->active;
while (transfer != NULL) { while (transfer != NULL) {
@ -202,7 +205,7 @@ void usb_queue_transfer_complete(usb_endpoint_t* const endpoint)
|| status & USB_TD_DTD_TOKEN_STATUS_BUFFER_ERROR || status & USB_TD_DTD_TOKEN_STATUS_BUFFER_ERROR
|| status & USB_TD_DTD_TOKEN_STATUS_TRANSACTION_ERROR) { || status & USB_TD_DTD_TOKEN_STATUS_TRANSACTION_ERROR) {
// TODO: Uh oh, do something useful here // TODO: Uh oh, do something useful here
while (1); while (1) {}
} }
// Still not finished // Still not finished

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@ -104,7 +104,7 @@ void w25q80bv_get_unique_id(w25q80bv_driver_t* const drv, w25q80bv_unique_id_t*
void w25q80bv_wait_while_busy(w25q80bv_driver_t* const drv) void w25q80bv_wait_while_busy(w25q80bv_driver_t* const drv)
{ {
while (w25q80bv_get_status(drv) & W25Q80BV_STATUS_BUSY); while (w25q80bv_get_status(drv) & W25Q80BV_STATUS_BUSY) {}
} }
void w25q80bv_write_enable(w25q80bv_driver_t* const drv) void w25q80bv_write_enable(w25q80bv_driver_t* const drv)
@ -113,7 +113,7 @@ void w25q80bv_write_enable(w25q80bv_driver_t* const drv)
uint8_t data[] = { W25Q80BV_WRITE_ENABLE }; uint8_t data[] = { W25Q80BV_WRITE_ENABLE };
spi_bus_transfer(drv->bus, data, ARRAY_SIZE(data)); spi_bus_transfer(drv->bus, data, ARRAY_SIZE(data));
while (!(w25q80bv_get_status(drv) & W25Q80BV_STATUS_WEL)); while (!(w25q80bv_get_status(drv) & W25Q80BV_STATUS_WEL)) {}
} }
void w25q80bv_chip_erase(w25q80bv_driver_t* const drv) void w25q80bv_chip_erase(w25q80bv_driver_t* const drv)

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@ -56,7 +56,7 @@ static void refill_cpld_buffer(void)
); );
// Wait until transfer finishes // Wait until transfer finishes
while (cpld_wait); while (cpld_wait) {}
} }
void cpld_update(void) void cpld_update(void)
@ -78,7 +78,7 @@ void cpld_update(void)
{ {
/* LED3 (Red) steady on error */ /* LED3 (Red) steady on error */
led_on(LED3); led_on(LED3);
while (1); while (1) {}
} }
} }

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@ -38,7 +38,7 @@ void m0_set_mode(enum m0_mode mode)
SGPIO_SET_STATUS_1 = (1 << SGPIO_SLICE_A); SGPIO_SET_STATUS_1 = (1 << SGPIO_SLICE_A);
// Wait for M0 to acknowledge by clearing the flag. // Wait for M0 to acknowledge by clearing the flag.
while (m0_state.requested_mode & M0_REQUEST_FLAG); while (m0_state.requested_mode & M0_REQUEST_FLAG) {}
} }
usb_request_status_t usb_vendor_request_get_m0_state( usb_request_status_t usb_vendor_request_get_m0_state(

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@ -433,5 +433,5 @@ void off_mode(uint32_t seq)
{ {
hackrf_ui()->set_transceiver_mode(TRANSCEIVER_MODE_OFF); hackrf_ui()->set_transceiver_mode(TRANSCEIVER_MODE_OFF);
while (transceiver_request.seq == seq); while (transceiver_request.seq == seq) {}
} }