Move PLL1/M4 CLK up to full speed (204MHz) in two steps, according to UM chapter 11.2.1.
This commit is contained in:
@ -149,23 +149,12 @@ void cpu_clock_init(void)
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| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_XTAL);
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| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_XTAL);
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/* use XTAL_OSC as clock source for PLL1 */
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/* use XTAL_OSC as clock source for PLL1 */
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CGU_PLL1_CTRL = (CGU_PLL1_CTRL_AUTOBLOCK
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/* Start PLL1 at 12MHz * 17 / 2 = 102MHz. */
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| (CGU_SRC_XTAL << CGU_PLL1_CTRL_CLK_SEL_SHIFT));
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CGU_PLL1_CTRL = CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL)
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| CGU_PLL1_CTRL_PSEL(1)
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/* configure PLL1 to produce 204 MHz clock from 12 MHz XTAL_OSC */
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| CGU_PLL1_CTRL_NSEL(0)
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/* not sure why, but it doesn't work without the following line */
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| CGU_PLL1_CTRL_MSEL(16)
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CGU_PLL1_CTRL &= ~(CGU_PLL1_CTRL_BYPASS
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| CGU_PLL1_CTRL_PD;
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| CGU_PLL1_CTRL_FBSEL
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| CGU_PLL1_CTRL_DIRECT
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| CGU_PLL1_CTRL_DIRECT
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| (0x3 << CGU_PLL1_CTRL_PSEL_SHIFT)
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| (0x3 << CGU_PLL1_CTRL_NSEL_SHIFT)
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| (0xFF << CGU_PLL1_CTRL_MSEL_SHIFT));
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CGU_PLL1_CTRL |= (CGU_PLL1_CTRL_FBSEL
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| CGU_PLL1_CTRL_DIRECT
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| (0 << CGU_PLL1_CTRL_PSEL_SHIFT)
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| (0 << CGU_PLL1_CTRL_NSEL_SHIFT)
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| (16 << CGU_PLL1_CTRL_MSEL_SHIFT));
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/* power on PLL1 and wait until stable */
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/* power on PLL1 and wait until stable */
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CGU_PLL1_CTRL &= ~CGU_PLL1_CTRL_PD;
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CGU_PLL1_CTRL &= ~CGU_PLL1_CTRL_PD;
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@ -174,6 +163,15 @@ void cpu_clock_init(void)
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/* use PLL1 as clock source for BASE_M4_CLK (CPU) */
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/* use PLL1 as clock source for BASE_M4_CLK (CPU) */
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CGU_BASE_M4_CLK = CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_PLL1);
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CGU_BASE_M4_CLK = CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_PLL1);
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/* Move PLL1 up to 12MHz * 17 = 204MHz. */
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CGU_PLL1_CTRL = CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL)
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| CGU_PLL1_CTRL_PSEL(0)
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| CGU_PLL1_CTRL_NSEL(0)
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| CGU_PLL1_CTRL_MSEL(16);
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/* wait until stable */
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while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK));
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/* use XTAL_OSC as clock source for PLL0USB */
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/* use XTAL_OSC as clock source for PLL0USB */
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CGU_PLL0USB_CTRL = CGU_PLL0USB_CTRL_PD
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CGU_PLL0USB_CTRL = CGU_PLL0USB_CTRL_PD
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| CGU_PLL0USB_CTRL_AUTOBLOCK
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| CGU_PLL0USB_CTRL_AUTOBLOCK
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