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Turned off integer-only for the PLLs too. Perhaps the docs have those bits flipped.

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Michael Ossmann
2012-05-01 10:20:45 -06:00
parent 580d6f3948
commit aa4d0a442a
1 changed files with 2 additions and 2 deletions
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4
hardware/test/si5351-configure.py
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@ -113,7 +113,7 @@ write_registers(3, 0xFF)
write_registers(9, 0xFF)
# Power down all CLKx
write_registers(16, (0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0xC0, 0xC0))
write_registers(16, (0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80))
# Register 183: Crystal Internal Load Capacitance
# Reads as 0xE4 on power-up
@ -197,7 +197,7 @@ write_registers(92, 0x00)
# CLK4_INV=0 (not inverted)
# CLK4_SRC=3 (MS4 as input source)
# CLK4_IDRV=3 (8mA)
write_registers(16, (0x0F, 0x0B, 0x0B, 0x0B, 0x0F, 0x80, 0xC0, 0xC0))
write_registers(16, (0x0F, 0x0B, 0x0B, 0x0B, 0x0F, 0x80, 0x80, 0x80))
# Enable CLK outputs 0, 1, 4 only.
write_registers(3, 0xFF ^ 0b00011111)