From a975fbc5770e00af20173b77fb14f730d9a884d4 Mon Sep 17 00:00:00 2001 From: Jared Boone Date: Thu, 27 Sep 2012 19:29:43 -0700 Subject: [PATCH] Replaced apparently incorrect PLL0USB MDIV and NP_DIV values with values straight out of the User Manual's table 94. --- firmware/common/hackrf_core.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/firmware/common/hackrf_core.c b/firmware/common/hackrf_core.c index 46fb76bd..8686aedc 100644 --- a/firmware/common/hackrf_core.c +++ b/firmware/common/hackrf_core.c @@ -179,12 +179,9 @@ void cpu_clock_init(void) while (CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK); /* configure PLL0USB to produce 480 MHz clock from 12 MHz XTAL_OSC */ - CGU_PLL0USB_MDIV = CGU_PLL0USB_MDIV_MDEC(0x07FFA) - | CGU_PLL0USB_MDIV_SELP(0x0B) - | CGU_PLL0USB_MDIV_SELI(0x10) - | CGU_PLL0USB_MDIV_SELR(0x0); - CGU_PLL0USB_NP_DIV = CGU_PLL0USB_NP_DIV_PDEC(98) - | CGU_PLL0USB_NP_DIV_NDEC(514); + /* Values from User Manual v1.4 Table 94, for 12MHz oscillator. */ + CGU_PLL0USB_MDIV = 0x06167FFA; + CGU_PLL0USB_NP_DIV = 0x00302062; CGU_PLL0USB_CTRL |= (CGU_PLL0USB_CTRL_PD | CGU_PLL0USB_CTRL_DIRECTI | CGU_PLL0USB_CTRL_DIRECTO