disable si clock to lpc
leaving it on but unused causes major spurs to appear all over the place..
This commit is contained in:
@ -139,8 +139,8 @@ void si5351c_configure_pll1_multisynth()
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//init plla and pllb to (0x0e00+512)/128*25mhz xtal = 800mhz -> int mode
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//init plla and pllb to (0x0e00+512)/128*25mhz xtal = 800mhz -> int mode
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uint8_t data[] = { 26, 0x00, 0x01, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00 };
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uint8_t data[] = { 26, 0x00, 0x01, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00 };
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si5351c_write(data, sizeof(data));
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si5351c_write(data, sizeof(data));
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data[0] =34;// pllb
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//~ data[0] =34;// pllb
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si5351c_write(data, sizeof(data));
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//~ si5351c_write(data, sizeof(data));
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}
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}
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void si5351c_configure_multisynth(const uint_fast8_t ms_number,
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void si5351c_configure_multisynth(const uint_fast8_t ms_number,
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@ -230,14 +230,14 @@ void si5351c_configure_clock_control()
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void si5351c_configure_clock_control()
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void si5351c_configure_clock_control()
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{
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{
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uint8_t data[] = {16
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uint8_t data[] = {16
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,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(SI5351C_CLK_PLL_SRC_B) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA)
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,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(SI5351C_CLK_PLL_SRC_A) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA)
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,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(SI5351C_CLK_PLL_SRC_B) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA)
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,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(SI5351C_CLK_PLL_SRC_A) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA)
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,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(SI5351C_CLK_PLL_SRC_B) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA)
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,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(SI5351C_CLK_PLL_SRC_A) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA)
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,SI5351C_CLK_POWERDOWN /*not connected, clock out*/
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,SI5351C_CLK_POWERDOWN /*not connected, clock out*/
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,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(SI5351C_CLK_PLL_SRC_B) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA)
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,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(SI5351C_CLK_PLL_SRC_A) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA)
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,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(SI5351C_CLK_PLL_SRC_B) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA)
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,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(SI5351C_CLK_PLL_SRC_A) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA)
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,SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/
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,SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/
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,SI5351C_CLK_INT_MODE/* pllb int mode*/| SI5351C_CLK_PLL_SRC(SI5351C_CLK_PLL_SRC_A) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA)
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,SI5351C_CLK_POWERDOWN/* pllb int mode*/| SI5351C_CLK_PLL_SRC(SI5351C_CLK_PLL_SRC_A) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA)
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};
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};
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si5351c_write(data, sizeof(data));
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si5351c_write(data, sizeof(data));
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}
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}
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@ -246,6 +246,6 @@ void si5351c_configure_clock_control()
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/* Enable CLK outputs 0, 1, 2, 4, 5, 7 only. */
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/* Enable CLK outputs 0, 1, 2, 4, 5, 7 only. */
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void si5351c_enable_clock_outputs()
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void si5351c_enable_clock_outputs()
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{
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{
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uint8_t data[] = { 3, 0x48 };
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uint8_t data[] = { 3, 0xC8 };
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si5351c_write(data, sizeof(data));
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si5351c_write(data, sizeof(data));
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}
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}
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