diff --git a/doc/wiki/hardware/modifications/sgpio-gclk2-reroute.jpg b/doc/wiki/hardware/modifications/sgpio-gclk2-reroute.jpg new file mode 100644 index 00000000..bf06e630 Binary files /dev/null and b/doc/wiki/hardware/modifications/sgpio-gclk2-reroute.jpg differ diff --git a/doc/wiki/hardware/modifications/sgpio-p1_12-cut-trace.jpg b/doc/wiki/hardware/modifications/sgpio-p1_12-cut-trace.jpg new file mode 100644 index 00000000..b97aa5a6 Binary files /dev/null and b/doc/wiki/hardware/modifications/sgpio-p1_12-cut-trace.jpg differ diff --git a/firmware/common/hackrf_core.c b/firmware/common/hackrf_core.c index ee991b27..67b673a0 100644 --- a/firmware/common/hackrf_core.c +++ b/firmware/common/hackrf_core.c @@ -24,6 +24,9 @@ #include "si5351c.h" #include #include +#include +#include +#include #ifdef JELLYBEAN @@ -54,10 +57,10 @@ void cpu_clock_init(void) /* MS0/CLK1 is the source for the MAX5864 codec. */ si5351c_configure_multisynth(1, 4608, 0, 1, 2); /* 10MHz */ - /* MS0/CLK2 is the source for the CPLD clock. */ - si5351c_configure_multisynth(2, 4608, 0, 1, 1); /* 20MHz */ + /* MS0/CLK2 is the source for the CPLD codec clock (same as CLK1). */ + si5351c_configure_multisynth(2, 4608, 0, 1, 2); /* 10MHz */ - /* MS0/CLK3 is the source for the CPLD clock (inverted). */ + /* MS0/CLK3 is the source for the SGPIO clock. */ si5351c_configure_multisynth(3, 4608, 0, 1, 1); /* 20MHz */ /* MS4/CLK4 is the source for the LPC43xx microcontroller. */ @@ -147,4 +150,58 @@ void cpu_clock_init(void) | (CGU_SRC_PLL0USB << CGU_BASE_CLK_SEL_SHIFT)); } +void ssp1_init(void) +{ + /* + * Configure CS_AD pin to keep the MAX5864 SPI disabled while we use the + * SPI bus for the MAX2837. FIXME: this should probably be somewhere else. + */ + scu_pinmux(SCU_AD_CS, SCU_GPIO_FAST); + GPIO_SET(PORT_AD_CS) = PIN_AD_CS; + GPIO_DIR(PORT_AD_CS) |= PIN_AD_CS; + + scu_pinmux(SCU_XCVR_CS, SCU_GPIO_FAST); + GPIO_SET(PORT_XCVR_CS) = PIN_XCVR_CS; + GPIO_DIR(PORT_XCVR_CS) |= PIN_XCVR_CS; + + /* Configure SSP1 Peripheral (to be moved later in SSP driver) */ + scu_pinmux(SCU_SSP1_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5)); + scu_pinmux(SCU_SSP1_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5)); + scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1)); +} + +void ssp1_set_mode_max2837(void) +{ + /* FIXME speed up once everything is working reliably */ + const uint8_t serial_clock_rate = 32; + const uint8_t clock_prescale_rate = 128; + + ssp_init(SSP1_NUM, + SSP_DATA_16BITS, + SSP_FRAME_SPI, + SSP_CPOL_0_CPHA_0, + serial_clock_rate, + clock_prescale_rate, + SSP_MODE_NORMAL, + SSP_MASTER, + SSP_SLAVE_OUT_ENABLE); +} + +void ssp1_set_mode_max5864(void) +{ + /* FIXME speed up once everything is working reliably */ + const uint8_t serial_clock_rate = 32; + const uint8_t clock_prescale_rate = 128; + + ssp_init(SSP1_NUM, + SSP_DATA_8BITS, + SSP_FRAME_SPI, + SSP_CPOL_0_CPHA_0, + serial_clock_rate, + clock_prescale_rate, + SSP_MODE_NORMAL, + SSP_MASTER, + SSP_SLAVE_OUT_ENABLE); +} + #endif diff --git a/firmware/common/hackrf_core.h b/firmware/common/hackrf_core.h index 7b4c7fde..8121ff71 100644 --- a/firmware/common/hackrf_core.h +++ b/firmware/common/hackrf_core.h @@ -75,7 +75,7 @@ extern "C" #define SCU_PINMUX_SGPIO5 (P6_6) #define SCU_PINMUX_SGPIO6 (P2_2) #define SCU_PINMUX_SGPIO7 (P1_0) -#define SCU_PINMUX_SGPIO8 (P9_6) +#define SCU_PINMUX_SGPIO8 (P1_12) #define SCU_PINMUX_SGPIO9 (P4_3) #define SCU_PINMUX_SGPIO10 (P1_14) #define SCU_PINMUX_SGPIO11 (P1_17) @@ -88,9 +88,10 @@ extern "C" #define SCU_XCVR_ENABLE (P4_6) /* GPIO2[6] on P4_6 */ #define SCU_XCVR_RXENABLE (P4_5) /* GPIO2[5] on P4_5 */ #define SCU_XCVR_TXENABLE (P4_4) /* GPIO2[4] on P4_4 */ +#define SCU_XCVR_CS (P1_20) /* GPIO0[15] on P1_20 */ -/* MAX5864 SPI chip select (CS_AD) GPIO PinMux */ -#define SCU_CS_AD (P5_7) /* GPIO2[7] on P5_7 */ +/* MAX5864 SPI chip select (AD_CS) GPIO PinMux */ +#define SCU_AD_CS (P5_7) /* GPIO2[7] on P5_7 */ /* RFFC5071 GPIO serial interface PinMux */ #define SCU_MIXER_ENX (P7_0) /* GPIO3[8] on P7_0 */ @@ -112,13 +113,15 @@ extern "C" #define PIN_EN1V8 (BIT6) /* GPIO3[6] on P6_10 */ #define PORT_EN1V8 (GPIO3) +#define PIN_XCVR_CS (BIT15) /* GPIO0[15] on P1_20 */ +#define PORT_XCVR_CS (GPIO0) /* PORT for CS */ #define PIN_XCVR_ENABLE (BIT6) /* GPIO2[6] on P4_6 */ #define PIN_XCVR_RXENABLE (BIT5) /* GPIO2[5] on P4_5 */ #define PIN_XCVR_TXENABLE (BIT4) /* GPIO2[4] on P4_4 */ #define PORT_XCVR_ENABLE (GPIO2) /* PORT for ENABLE, TXENABLE, RXENABLE */ -#define PIN_CS_AD (BIT7) /* GPIO2[7] on P5_7 */ -#define PORT_CS_AD (GPIO2) /* PORT for CS_AD */ +#define PIN_AD_CS (BIT7) /* GPIO2[7] on P5_7 */ +#define PORT_AD_CS (GPIO2) /* PORT for AD_CS */ #define PIN_MIXER_ENX (BIT8) /* GPIO3[8] on P7_0 */ #define PIN_MIXER_SCLK (BIT9) /* GPIO3[9] on P7_1 */ @@ -152,6 +155,9 @@ extern "C" #endif void cpu_clock_init(void); +void ssp1_init(void); +void ssp1_set_mode_max2837(void); +void ssp1_set_mode_max5864(void); #ifdef __cplusplus } diff --git a/firmware/common/max2837.c b/firmware/common/max2837.c index f5e709b7..a9e8120d 100644 --- a/firmware/common/max2837.c +++ b/firmware/common/max2837.c @@ -86,10 +86,6 @@ void max2837_setup(void) { LOG("# max2837_setup\n"); #if !defined TEST - /* FIXME speed up once everything is working reliably */ - const uint8_t serial_clock_rate = 32; - const uint8_t clock_prescale_rate = 128; - /* Configure XCVR_CTL GPIO pins. */ scu_pinmux(SCU_XCVR_ENABLE, SCU_GPIO_FAST); scu_pinmux(SCU_XCVR_RXENABLE, SCU_GPIO_FAST); @@ -101,30 +97,6 @@ void max2837_setup(void) /* disable everything */ gpio_clear(PORT_XCVR_ENABLE, (PIN_XCVR_ENABLE | PIN_XCVR_RXENABLE | PIN_XCVR_TXENABLE)); - - /* - * Configure CS_AD pin to keep the MAX5864 SPI disabled while we use the - * SPI bus for the MAX2837. FIXME: this should probably be somewhere else. - */ - scu_pinmux(SCU_CS_AD, SCU_GPIO_FAST); - GPIO2_DIR |= PIN_CS_AD; - gpio_set(PORT_CS_AD, PIN_CS_AD); - - /* Configure SSP1 Peripheral (to be moved later in SSP driver) */ - scu_pinmux(SCU_SSP1_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5)); - scu_pinmux(SCU_SSP1_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5)); - scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1)); - scu_pinmux(SCU_SSP1_SSEL, (SCU_SSP_IO | SCU_CONF_FUNCTION1)); - - ssp_init(SSP1_NUM, - SSP_DATA_16BITS, - SSP_FRAME_SPI, - SSP_CPOL_0_CPHA_0, - serial_clock_rate, - clock_prescale_rate, - SSP_MODE_NORMAL, - SSP_MASTER, - SSP_SLAVE_OUT_ENABLE); #endif max2837_init(); @@ -145,6 +117,9 @@ void max2837_setup(void) /* SPI register read. */ uint16_t max2837_spi_read(uint8_t r) { + gpio_clear(PORT_XCVR_CS, PIN_XCVR_CS); + // FIXME: Unimplemented. + gpio_set(PORT_XCVR_CS, PIN_XCVR_CS); return 0; } @@ -157,7 +132,9 @@ void max2837_spi_write(uint8_t r, uint16_t v) { #elif DEBUG LOG("0x%03x -> reg%d\n", v, r); #else + gpio_clear(PORT_XCVR_CS, PIN_XCVR_CS); ssp_write(SSP1_NUM, (uint16_t)((r << 10) | (v & 0x3ff))); + gpio_set(PORT_XCVR_CS, PIN_XCVR_CS); #endif } @@ -215,6 +192,14 @@ void max2837_tx(void) #endif } +void max2837_rx(void) +{ + LOG("# max2837_rx\n"); +#if !defined TEST + gpio_set(PORT_XCVR_ENABLE, PIN_XCVR_RXENABLE); +#endif +} + void max2837_stop(void) { LOG("# max2837_stop\n"); diff --git a/firmware/common/max2837.h b/firmware/common/max2837.h index 25878bb9..50cf38d7 100644 --- a/firmware/common/max2837.h +++ b/firmware/common/max2837.h @@ -42,5 +42,6 @@ extern void max2837_stop(void); extern void max2837_set_frequency(uint32_t freq); extern void max2837_tx(void); +extern void max2837_rx(void); #endif // __MAX2837_H diff --git a/firmware/common/si5351c.c b/firmware/common/si5351c.c index 6708f748..26b9d2de 100644 --- a/firmware/common/si5351c.c +++ b/firmware/common/si5351c.c @@ -188,7 +188,7 @@ void si5351c_configure_multisynth(const uint_fast8_t ms_number, * CLK3_PDN=0 (powered up) * MS3_INT=1 (integer mode) * MS3_SRC=0 (PLLA as source for MultiSynth 3) - * CLK3_INV=1 (inverted) + * CLK3_INV=0 (inverted) * CLK3_SRC=2 (MS0 as input source) * CLK3_IDRV=3 (8mA) * CLK4: @@ -208,7 +208,7 @@ void si5351c_configure_multisynth(const uint_fast8_t ms_number, */ void si5351c_configure_clock_control() { - uint8_t data[] = { 16, 0x4F, 0x4B, 0x4B, 0x5B, 0x0F, 0x4F, 0xC0, 0xC0 }; + uint8_t data[] = { 16, 0x4F, 0x4B, 0x4B, 0x4B, 0x0F, 0x4F, 0xC0, 0xC0 }; si5351c_write(data, sizeof(data)); } diff --git a/firmware/mixertx/mixertx.c b/firmware/mixertx/mixertx.c index a1c15c06..ea41bb21 100644 --- a/firmware/mixertx/mixertx.c +++ b/firmware/mixertx/mixertx.c @@ -61,9 +61,11 @@ int main(void) pin_setup(); gpio_set(PORT_EN1V8, PIN_EN1V8); /* 1V8 on */ cpu_clock_init(); + ssp1_init(); gpio_set(PORT_LED1_3, (PIN_LED1)); /* LED1 on */ + ssp1_set_mode_max2837(); max2837_setup(); rffc5071_init(); rffc5071_reg_write(RFFC5071_GPO, 0x0001); /* PLL lock output on GPO4 */ diff --git a/firmware/sgpio/sgpio.c b/firmware/sgpio/sgpio.c index 26552828..c270592c 100644 --- a/firmware/sgpio/sgpio.c +++ b/firmware/sgpio/sgpio.c @@ -45,10 +45,11 @@ void pin_setup(void) { GPIO6_DIR = 0; GPIO7_DIR = 0; - /* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */GPIO2_DIR |= (PIN_LED1 - | PIN_LED2 | PIN_LED3); + /* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */ + GPIO2_DIR |= (PIN_LED1 | PIN_LED2 | PIN_LED3); - /* GPIO3[6] on P6_10 as output. */GPIO3_DIR |= PIN_EN1V8; + /* GPIO3[6] on P6_10 as output. */ + GPIO3_DIR |= PIN_EN1V8; /* Configure SSP1 Peripheral (to be moved later in SSP driver) */ scu_pinmux(SCU_SSP1_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5)); @@ -67,10 +68,10 @@ void release_cpld_jtag_pins() { scu_pinmux(SCU_PINMUX_CPLD_TMS, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0); scu_pinmux(SCU_PINMUX_CPLD_TDI, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0); - GPIO_CLR(PORT_CPLD_TDO) = PIN_CPLD_TDO; - GPIO_CLR(PORT_CPLD_TCK) = PIN_CPLD_TCK; - GPIO_CLR(PORT_CPLD_TMS) = PIN_CPLD_TMS; - GPIO_CLR(PORT_CPLD_TDI) = PIN_CPLD_TDI; + GPIO_DIR(PORT_CPLD_TDO) &= ~PIN_CPLD_TDO; + GPIO_DIR(PORT_CPLD_TCK) &= ~PIN_CPLD_TCK; + GPIO_DIR(PORT_CPLD_TMS) &= ~PIN_CPLD_TMS; + GPIO_DIR(PORT_CPLD_TDI) &= ~PIN_CPLD_TDI; } void configure_sgpio_pin_functions() { @@ -131,7 +132,7 @@ void test_sgpio_interface() { } } -void configure_sgpio() { +void configure_sgpio_test_tx() { // Disable all counters during configuration SGPIO_CTRL_ENABLE = 0; @@ -144,9 +145,11 @@ void configure_sgpio() { // Enable SGPIO pin outputs. SGPIO_GPIO_OENREG = - (1L << 11) | // direction + (1L << 11) | // direction: TX: data to CPLD (1L << 10) | // disable - 0xFF; + (0L << 9) | // capture + (0L << 8) | // clock + 0xFF; // data: output SGPIO_OUT_MUX_CFG( 8) = 0; // SGPIO: Input: clock SGPIO_OUT_MUX_CFG( 9) = 0; // SGPIO: Input: qualifier @@ -183,42 +186,100 @@ void configure_sgpio() { SGPIO_PRESET(SGPIO_SLICE_A) = 0; SGPIO_COUNT(SGPIO_SLICE_A) = 0; SGPIO_POS(SGPIO_SLICE_A) = (0x3L << 8) | (0x3L << 0); - SGPIO_REG(SGPIO_SLICE_A) = 0xFF00FF00; // Primary output data register - SGPIO_REG_SS(SGPIO_SLICE_A) = 0xFF00FF00; // Shadow output data register - /* - // Slice D (clock for Slice A) - LPC_SGPIO->SGPIO_MUX_CFG[3] = - (0L << 12) | // CONCAT_ORDER = 0 (self-loop) - (1L << 11) | // CONCAT_ENABLE = 1 (concatenate data) - (0L << 9) | // QUALIFIER_SLICE_MODE = X - (0L << 7) | // QUALIFIER_PIN_MODE = X - (0L << 5) | // QUALIFIER_MODE = 0 (enable) - (0L << 3) | // CLK_SOURCE_SLICE_MODE = 0, slice D - (0L << 1) | // CLK_SOURCE_PIN_MODE = X - (0L << 0); // EXT_CLK_ENABLE = 0, internal clock signal (slice) + SGPIO_REG(SGPIO_SLICE_A) = 0x80808080; // Primary output data register + SGPIO_REG_SS(SGPIO_SLICE_A) = 0x80808080; // Shadow output data register - LPC_SGPIO->SLICE_MUX_CFG[3] = + // Start SGPIO operation by enabling slice clocks. + SGPIO_CTRL_ENABLE = + (1L << SGPIO_SLICE_A) + ; + + // LSB goes out first, samples are 0x + volatile uint32_t buffer[] = { + 0xda808080, + 0xda80ff80, + 0x26808080, + 0x26800180, + }; + uint32_t i = 0; + + // Enable codec data stream. + SGPIO_GPIO_OUTREG &= ~(1L << 10); + + while(true) { + while(SGPIO_STATUS_1 == 0); + SGPIO_REG_SS(SGPIO_SLICE_A) = buffer[(i++) & 3]; + SGPIO_CLR_STATUS_1 = 1; + } +} + +void configure_sgpio_test_rx() { + // Disable all counters during configuration + SGPIO_CTRL_ENABLE = 0; + + configure_sgpio_pin_functions(); + + // Set SGPIO output values. + SGPIO_GPIO_OUTREG = + (0L << 11) | // direction + (1L << 10); // disable + + // Enable SGPIO pin outputs. + SGPIO_GPIO_OENREG = + (1L << 11) | // direction: RX: data from CPLD + (1L << 10) | // disable + (0L << 9) | // capture + (0L << 8) | // clock + 0x00; // data: input + + SGPIO_OUT_MUX_CFG( 8) = 0; // SGPIO: Input: clock + SGPIO_OUT_MUX_CFG( 9) = 0; // SGPIO: Input: qualifier + SGPIO_OUT_MUX_CFG(10) = (0L << 4) | (4L << 0); // GPIO: Output: disable + SGPIO_OUT_MUX_CFG(11) = (0L << 4) | (4L << 0); // GPIO: Output: direction + + for(uint_fast8_t i=0; i<8; i++) { + SGPIO_OUT_MUX_CFG(i) = + (0L << 4) | // P_OE_CFG = 0 + (9L << 0); // P_OUT_CFG = 9, dout_doutm8a (8-bit mode 8a) + } + + // Slice A + SGPIO_MUX_CFG(SGPIO_SLICE_A) = + (0L << 12) | // CONCAT_ORDER = X + (0L << 11) | // CONCAT_ENABLE = 0 (concatenate data) + (0L << 9) | // QUALIFIER_SLICE_MODE = X + (1L << 7) | // QUALIFIER_PIN_MODE = 1 (SGPIO9) + (3L << 5) | // QUALIFIER_MODE = 3 (external SGPIO pin) + (0L << 3) | // CLK_SOURCE_SLICE_MODE = X + (0L << 1) | // CLK_SOURCE_PIN_MODE = 0 (SGPIO8) + (1L << 0); // EXT_CLK_ENABLE = 1, external clock signal (slice) + + SGPIO_SLICE_MUX_CFG(SGPIO_SLICE_A) = (0L << 8) | // INV_QUALIFIER = 0 (use normal qualifier) - (0L << 6) | // PARALLEL_MODE = 0 (shift 1 bit per clock) + (3L << 6) | // PARALLEL_MODE = 3 (shift 8 bits per clock) (0L << 4) | // DATA_CAPTURE_MODE = 0 (detect rising edge) - (0L << 3) | // INV_OUT_CLK = 0 (normal clock) - (0L << 2) | // CLKGEN_MODE = 0 (use clock from COUNTER) + (0L << 3) | // INV_OUT_CLK = X + (1L << 2) | // CLKGEN_MODE = 1 (use external pin clock) (0L << 1) | // CLK_CAPTURE_MODE = 0 (use rising clock edge) (0L << 0); // MATCH_MODE = 0 (do not match data) - LPC_SGPIO->PRESET[3] = 0; - LPC_SGPIO->COUNT[3] = 0; - LPC_SGPIO->POS[3] = (0x1FL << 8) | (0x1FL << 0); - LPC_SGPIO->REG[0] = 0xAAAAAAAA; // Primary output data register - LPC_SGPIO->REG_SS[0] = 0xAAAAAAAA; // Shadow output data register - */ - // Start SGPIO operation by enabling slice clocks. - SGPIO_CTRL_ENABLE = - (1L << 0) // Slice A - ; + SGPIO_PRESET(SGPIO_SLICE_A) = 0; + SGPIO_COUNT(SGPIO_SLICE_A) = 0; + SGPIO_POS(SGPIO_SLICE_A) = (3 << 8) | (3 << 0); + SGPIO_REG(SGPIO_SLICE_A) = 0xCAFEBABE; // Primary output data register + SGPIO_REG_SS(SGPIO_SLICE_A) = 0xDEADBEEF; // Shadow output data register + + volatile uint32_t buffer[4096]; + uint32_t i = 0; // Enable codec data stream. SGPIO_GPIO_OUTREG &= ~(1L << 10); + + while(true) { + while(SGPIO_STATUS_1 == 0); + SGPIO_CLR_STATUS_1 = 1; + buffer[i++ & 4095] = SGPIO_REG_SS(SGPIO_SLICE_A); + } } int main(void) { @@ -235,7 +296,7 @@ int main(void) { gpio_set(PORT_LED1_3, (PIN_LED1 | PIN_LED2 | PIN_LED3)); /* LEDs on */ //test_sgpio_interface(); - configure_sgpio(); + configure_sgpio_test_rx(); while (1) { diff --git a/firmware/simpletx/simpletx.c b/firmware/simpletx/simpletx.c index f57c7b0c..7d61cb6a 100644 --- a/firmware/simpletx/simpletx.c +++ b/firmware/simpletx/simpletx.c @@ -60,9 +60,11 @@ int main(void) pin_setup(); gpio_set(PORT_EN1V8, PIN_EN1V8); /* 1V8 on */ cpu_clock_init(); - + ssp1_init(); + gpio_set(PORT_LED1_3, (PIN_LED1)); /* LED1 on */ + ssp1_set_mode_max2837(); max2837_setup(); gpio_set(PORT_LED1_3, (PIN_LED2)); /* LED2 on */ max2837_set_frequency(freq); diff --git a/hardware/jellybean/sgpio_if/sgpio_if.svf b/hardware/jellybean/sgpio_if/sgpio_if.svf index 19ea35b4..afe8e3a2 100755 --- a/hardware/jellybean/sgpio_if/sgpio_if.svf +++ b/hardware/jellybean/sgpio_if/sgpio_if.svf @@ -1,5 +1,5 @@ // Created using Xilinx Cse Software [ISE - 13.4] -// Date: Sat Jun 09 22:05:18 2012 +// Date: Thu Jun 14 19:14:18 2012 TRST OFF; ENDIR IDLE; @@ -172,19 +172,19 @@ SDR 281 TDI (0042f9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff RUNTEST 10000 TCK; SDR 281 TDI (006201fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe7c) ; RUNTEST 10000 TCK; -SDR 281 TDI (0163c1fffffffffffffffffffffffffffffddf7ffffffffefffffffffffffffffffffe2f) ; +SDR 281 TDI (0163c1fffffffffffffffffffffffffffffddf7ffffffffefffffffffffffffffffffe4f) ; RUNTEST 10000 TCK; SDR 281 TDI (01e2f9fffffffffffffffffffffffffffffd7f7fffffffbffffffffffffffffffffffe7c) ; RUNTEST 10000 TCK; SDR 281 TDI (00e201ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff01) ; RUNTEST 10000 TCK; -SDR 281 TDI (00a3c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe2f) ; +SDR 281 TDI (00a3c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe4f) ; RUNTEST 10000 TCK; SDR 281 TDI (01a2f9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe7c) ; RUNTEST 10000 TCK; SDR 281 TDI (012201fffffffffffffffffffffffffffffd7f7fffffffffffffffffffff7ffffffffe81) ; RUNTEST 10000 TCK; -SDR 281 TDI (0023c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe2f) ; +SDR 281 TDI (0023c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe4f) ; RUNTEST 10000 TCK; SDR 281 TDI (0032f9fffffffffffffffffffffffffffffd7f7fffffeffffffffffffffffffffffffe7c) ; RUNTEST 10000 TCK; @@ -192,7 +192,7 @@ SDR 281 TDI (013201fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff RUNTEST 10000 TCK; SDR 281 TDI (01b3c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) ; RUNTEST 10000 TCK; -SDR 281 TDI (00b2f9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe1d) ; +SDR 281 TDI (00b2f9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe7f) ; RUNTEST 10000 TCK; SDR 281 TDI (00f201fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe7c) ; RUNTEST 10000 TCK; @@ -200,9 +200,9 @@ SDR 281 TDI (01f3c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff RUNTEST 10000 TCK; SDR 281 TDI (0172f9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe1d) ; RUNTEST 10000 TCK; -SDR 281 TDI (007201ffffffffffffffffffffffffffffffe9e7fffffffffffffffffffffffffffffe7c) ; +SDR 281 TDI (007201ffffffffffffffffffffffffffffffe5e7fffffffffffffffffffffffffffffe7c) ; RUNTEST 10000 TCK; -SDR 281 TDI (0053c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe2f) ; +SDR 281 TDI (0053c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe4f) ; RUNTEST 10000 TCK; SDR 281 TDI (0152f9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe7c) ; RUNTEST 10000 TCK; @@ -210,29 +210,29 @@ SDR 281 TDI (01d201fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff RUNTEST 10000 TCK; SDR 281 TDI (00d3c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) ; RUNTEST 10000 TCK; -SDR 281 TDI (0092f9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe7f) ; +SDR 281 TDI (0092f9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe7d) ; RUNTEST 10000 TCK; SDR 281 TDI (019201fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe7c) ; RUNTEST 10000 TCK; -SDR 281 TDI (0113c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe2f) ; +SDR 281 TDI (0113c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe4f) ; RUNTEST 10000 TCK; SDR 281 TDI (0012f9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe7c) ; RUNTEST 10000 TCK; SDR 281 TDI (001a01fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe81) ; RUNTEST 10000 TCK; -SDR 281 TDI (011bc1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe2f) ; +SDR 281 TDI (011bc1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe4f) ; RUNTEST 10000 TCK; SDR 281 TDI (019af9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe7c) ; RUNTEST 10000 TCK; SDR 281 TDI (009a01fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe81) ; RUNTEST 10000 TCK; -SDR 281 TDI (00dbc1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe2f) ; +SDR 281 TDI (00dbc1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe4f) ; RUNTEST 10000 TCK; SDR 281 TDI (01daf9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe7c) ; RUNTEST 10000 TCK; SDR 281 TDI (015a01fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe81) ; RUNTEST 10000 TCK; -SDR 281 TDI (005bc1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe2f) ; +SDR 281 TDI (005bc1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe4f) ; RUNTEST 10000 TCK; SDR 281 TDI (007af9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe7c) ; RUNTEST 10000 TCK; @@ -250,11 +250,11 @@ SDR 281 TDI (013af9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff RUNTEST 10000 TCK; SDR 281 TDI (003a01fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe01) ; RUNTEST 10000 TCK; -SDR 281 TDI (002bd1fffff7ffffffffffffffffffffffebfefffffffffffffffffffffffffffffffe0f) ; +SDR 281 TDI (002bc9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) ; RUNTEST 10000 TCK; SDR 281 TDI (0128fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe1d) ; RUNTEST 10000 TCK; -SDR 281 TDI (01aa01fffffffffffffffffffffff7ffffebfefffffffffffffffffffffffffffffffe7c) ; +SDR 281 TDI (01aa01fffff7ffffffffffffffffffffffebfefffffffffffffffffffffffffffffffe7c) ; RUNTEST 10000 TCK; SDR 281 TDI (00abc1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) ; RUNTEST 10000 TCK; @@ -262,7 +262,7 @@ SDR 281 TDI (00ebf9fffffffffffffffff7fffffffffffbeefffffffffffffffffffffffffffff RUNTEST 10000 TCK; SDR 281 TDI (01e8f9fffbfffffffffffffffffffffffffbbefffffffffffffffffffffffffffffffe7c) ; RUNTEST 10000 TCK; -SDR 281 TDI (016bd1fffffffffff7fffffffffffffffffbeefffffffffffffffffffffffffffffffe0f) ; +SDR 281 TDI (016bc9fffffffffff7fffffffffffffffffbeefffffffffffffffffffffffffffffffe0f) ; RUNTEST 10000 TCK; SDR 281 TDI (0068e1ffffffffffffffffffffffffff7ffbbefffffffffffffffffffffffffffffffe1d) ; RUNTEST 10000 TCK; @@ -274,7 +274,7 @@ SDR 281 TDI (01cbf9ffffffffffffffffffffffffdffffbeefffffffffffffffffffffffffffff RUNTEST 10000 TCK; SDR 281 TDI (00c8f8fffffffffffffffffffffffffffffafefffffffffffffffffffffffffffffffe7c) ; RUNTEST 10000 TCK; -SDR 281 TDI (008bd1ffffffffffffff7ffffffffffffffbbefffffffffffffffffffffffffffffffe0f) ; +SDR 281 TDI (008bc9ffffffffffffff7ffffffffffffffbbefffffffffffffffffffffffffffffffe0f) ; RUNTEST 10000 TCK; SDR 281 TDI (0188e1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe1d) ; RUNTEST 10000 TCK; @@ -286,7 +286,7 @@ SDR 281 TDI (000ff9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff RUNTEST 10000 TCK; SDR 281 TDI (010cf9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe7c) ; RUNTEST 10000 TCK; -SDR 281 TDI (018fd1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) ; +SDR 281 TDI (018fc9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) ; RUNTEST 10000 TCK; SDR 281 TDI (008ce1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe1d) ; RUNTEST 10000 TCK; @@ -298,13 +298,13 @@ SDR 281 TDI (014ee1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff RUNTEST 10000 TCK; SDR 281 TDI (004cf9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe7c) ; RUNTEST 10000 TCK; -SDR 281 TDI (006fd1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) ; +SDR 281 TDI (006fc9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) ; RUNTEST 10000 TCK; SDR 281 TDI (016ce1fffffffffffffffffffffffffffffff9fffffffffffffffffffffffffffffffe7d) ; RUNTEST 10000 TCK; SDR 281 TDI (01eec5fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe01) ; RUNTEST 10000 TCK; -SDR 281 TDI (00efd1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) ; +SDR 281 TDI (00efc9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) ; RUNTEST 10000 TCK; SDR 281 TDI (00ace1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe7d) ; RUNTEST 10000 TCK; @@ -324,23 +324,23 @@ SDR 281 TDI (00bcf9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff RUNTEST 10000 TCK; SDR 281 TDI (00ffc1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) ; RUNTEST 10000 TCK; -SDR 281 TDI (01fef9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe7d) ; +SDR 281 TDI (01fff9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe7d) ; RUNTEST 10000 TCK; -SDR 281 TDI (017e05fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe01) ; +SDR 281 TDI (017cf9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe01) ; RUNTEST 10000 TCK; -SDR 281 TDI (007fd1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) ; +SDR 281 TDI (007fc9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) ; RUNTEST 10000 TCK; SDR 281 TDI (005ce1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe7d) ; RUNTEST 10000 TCK; SDR 281 TDI (015ec5fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe01) ; RUNTEST 10000 TCK; -SDR 281 TDI (01dfd1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) ; +SDR 281 TDI (01dfc9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) ; RUNTEST 10000 TCK; SDR 281 TDI (00dce1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe7d) ; RUNTEST 10000 TCK; SDR 281 TDI (009ec5fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe01) ; RUNTEST 10000 TCK; -SDR 281 TDI (019fd1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) ; +SDR 281 TDI (019fc9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) ; RUNTEST 10000 TCK; SDR 281 TDI (011ce1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe7d) ; RUNTEST 10000 TCK; @@ -457,7 +457,7 @@ SDR 7 TDI (58) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c1fffffffffffffffffffffffffffffddf7ffffffffefffffffffffffffffffffe2f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c1fffffffffffffffffffffffffffffddf7ffffffffefffffffffffffffffffffe4f) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -481,7 +481,7 @@ SDR 7 TDI (28) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe2f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe4f) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -505,7 +505,7 @@ SDR 7 TDI (08) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe2f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe4f) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -537,7 +537,7 @@ SDR 7 TDI (2c) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (02f9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe1d) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (02f9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe7f) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -569,7 +569,7 @@ SDR 7 TDI (1c) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (0201ffffffffffffffffffffffffffffffe9e7fffffffffffffffffffffffffffffe7c) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (0201ffffffffffffffffffffffffffffffe5e7fffffffffffffffffffffffffffffe7c) MASK ( 03fffffffffffffffffffffffffffffe001ff801ffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -577,7 +577,7 @@ SDR 7 TDI (14) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe2f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe4f) MASK ( 03fffffffffffffffffffffffffffffe001f8001ffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -609,7 +609,7 @@ SDR 7 TDI (24) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (02f9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe7f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (02f9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe7d) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -625,7 +625,7 @@ SDR 7 TDI (44) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe2f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe4f) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -649,7 +649,7 @@ SDR 7 TDI (46) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe2f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe4f) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -673,7 +673,7 @@ SDR 7 TDI (36) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe2f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe4f) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -697,7 +697,7 @@ SDR 7 TDI (16) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe2f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe4f) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -769,7 +769,7 @@ SDR 7 TDI (0a) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03d1fffff7ffffffffffffffffffffffebfefffffffffffffffffffffffffffffffe0f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -785,7 +785,7 @@ SDR 7 TDI (6a) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (0201fffffffffffffffffffffff7ffffebfefffffffffffffffffffffffffffffffe7c) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (0201fffff7ffffffffffffffffffffffebfefffffffffffffffffffffffffffffffe7c) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -817,7 +817,7 @@ SDR 7 TDI (5a) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03d1fffffffffff7fffffffffffffffffbeefffffffffffffffffffffffffffffffe0f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c9fffffffffff7fffffffffffffffffbeefffffffffffffffffffffffffffffffe0f) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -865,7 +865,7 @@ SDR 7 TDI (22) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03d1ffffffffffffff7ffffffffffffffbbefffffffffffffffffffffffffffffffe0f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c9ffffffffffffff7ffffffffffffffbbefffffffffffffffffffffffffffffffe0f) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -913,7 +913,7 @@ SDR 7 TDI (63) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03d1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -961,7 +961,7 @@ SDR 7 TDI (1b) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03d1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) MASK ( 03fffffffffffffffffffffffffffffe00000001ffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -985,7 +985,7 @@ SDR 7 TDI (3b) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03d1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) MASK ( 03fffffffffffffffffffffffffffffe00000001ffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -1065,7 +1065,7 @@ SDR 7 TDI (7f) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (02f9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe7d) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03f9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe7d) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -1073,7 +1073,7 @@ SDR 7 TDI (5f) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (0205fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe01) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (00f9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe01) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -1081,7 +1081,7 @@ SDR 7 TDI (1f) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03d1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -1105,7 +1105,7 @@ SDR 7 TDI (77) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03d1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -1129,7 +1129,7 @@ SDR 7 TDI (67) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03d1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -1338,7 +1338,7 @@ SDR 7 TDI (58) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c1fffffffffffffffffffffffffffffddf7ffffffffefffffffffffffffffffffe2f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c1fffffffffffffffffffffffffffffddf7ffffffffefffffffffffffffffffffe4f) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -1362,7 +1362,7 @@ SDR 7 TDI (28) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe2f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe4f) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -1386,7 +1386,7 @@ SDR 7 TDI (08) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe2f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe4f) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -1418,7 +1418,7 @@ SDR 7 TDI (2c) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (02f9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe1d) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (02f9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe7f) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -1450,7 +1450,7 @@ SDR 7 TDI (1c) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (0201ffffffffffffffffffffffffffffffe9e7fffffffffffffffffffffffffffffe7c) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (0201ffffffffffffffffffffffffffffffe5e7fffffffffffffffffffffffffffffe7c) MASK ( 03fffffffffffffffffffffffffffffe001ff801ffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -1458,7 +1458,7 @@ SDR 7 TDI (14) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe2f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe4f) MASK ( 03fffffffffffffffffffffffffffffe001f8001ffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -1490,7 +1490,7 @@ SDR 7 TDI (24) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (02f9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe7f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (02f9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe7d) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -1506,7 +1506,7 @@ SDR 7 TDI (44) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe2f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe4f) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -1530,7 +1530,7 @@ SDR 7 TDI (46) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe2f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe4f) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -1554,7 +1554,7 @@ SDR 7 TDI (36) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe2f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe4f) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -1578,7 +1578,7 @@ SDR 7 TDI (16) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe2f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe4f) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -1650,7 +1650,7 @@ SDR 7 TDI (0a) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03d1fffff7ffffffffffffffffffffffebfefffffffffffffffffffffffffffffffe0f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -1666,7 +1666,7 @@ SDR 7 TDI (6a) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (0201fffffffffffffffffffffff7ffffebfefffffffffffffffffffffffffffffffe7c) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (0201fffff7ffffffffffffffffffffffebfefffffffffffffffffffffffffffffffe7c) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -1698,7 +1698,7 @@ SDR 7 TDI (5a) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03d1fffffffffff7fffffffffffffffffbeefffffffffffffffffffffffffffffffe0f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c9fffffffffff7fffffffffffffffffbeefffffffffffffffffffffffffffffffe0f) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -1746,7 +1746,7 @@ SDR 7 TDI (22) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03d1ffffffffffffff7ffffffffffffffbbefffffffffffffffffffffffffffffffe0f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c9ffffffffffffff7ffffffffffffffbbefffffffffffffffffffffffffffffffe0f) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -1794,7 +1794,7 @@ SDR 7 TDI (63) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03d1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -1842,7 +1842,7 @@ SDR 7 TDI (1b) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03d1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) MASK ( 03fffffffffffffffffffffffffffffe00000001ffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -1866,7 +1866,7 @@ SDR 7 TDI (3b) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03d1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) MASK ( 03fffffffffffffffffffffffffffffe00000001ffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -1946,7 +1946,7 @@ SDR 7 TDI (7f) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (02f9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe7d) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03f9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe7d) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -1954,7 +1954,7 @@ SDR 7 TDI (5f) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (0205fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe01) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (00f9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe01) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -1962,7 +1962,7 @@ SDR 7 TDI (1f) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03d1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -1986,7 +1986,7 @@ SDR 7 TDI (77) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03d1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; @@ -2010,7 +2010,7 @@ SDR 7 TDI (67) SMASK (7f) ; RUNTEST DRPAUSE 20 TCK; ENDDR IDLE; RUNTEST IDLE 100 TCK; -SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03d1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) MASK ( +SDR 274 TDI (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) SMASK (03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (03c9fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe0f) MASK ( 03ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; RUNTEST 100 TCK; ENDDR DRPAUSE; diff --git a/hardware/jellybean/sgpio_if/top.ucf b/hardware/jellybean/sgpio_if/top.ucf index d57851ca..a593ec52 100755 --- a/hardware/jellybean/sgpio_if/top.ucf +++ b/hardware/jellybean/sgpio_if/top.ucf @@ -18,9 +18,9 @@ # the Free Software Foundation, Inc., 51 Franklin Street, # Boston, MA 02110-1301, USA. -NET "CODEC_CLK" LOC="22" |FAST |IOSTANDARD=LVCMOS18; -NET "CODEC_X2_CLK" LOC="23" |FAST |IOSTANDARD=LVCMOS18; -#NET "GCLK2" LOC="27" |FAST |IOSTANDARD=LVCMOS18; +NET "CODEC_CLK" LOC="23" |FAST |IOSTANDARD=LVCMOS18; +NET "CODEC_X2_CLK" LOC="27" |FAST |IOSTANDARD=LVCMOS18; +#NET "GCLK0" LOC="22" |FAST |IOSTANDARD=LVCMOS18; NET "CODEC_X2_CLK" TNM_NET = CODEC_X2_CLK; TIMESPEC TS_codec_x2_data = PERIOD "CODEC_X2_CLK" 50 ns; @@ -61,7 +61,7 @@ NET "B1AUX<9>" LOC="49" |FAST |IOSTANDARD=LVCMOS18; NET "HOST_DIRECTION" LOC="71" |FAST |IOSTANDARD=LVCMOS33; NET "HOST_DISABLE" LOC="76" |FAST |IOSTANDARD=LVCMOS33; NET "HOST_CAPTURE" LOC="91" |FAST |IOSTANDARD=LVCMOS33; -NET "HOST_CLK" LOC="68" |FAST |IOSTANDARD=LVCMOS33; +#NET "HOST_CLK" LOC="68" |FAST |IOSTANDARD=LVCMOS33; NET "HOST_DATA<7>" LOC="77" |FAST |IOSTANDARD=LVCMOS33; NET "HOST_DATA<6>" LOC="61" |FAST |IOSTANDARD=LVCMOS33; NET "HOST_DATA<5>" LOC="64" |FAST |IOSTANDARD=LVCMOS33; diff --git a/hardware/jellybean/sgpio_if/top.vhd b/hardware/jellybean/sgpio_if/top.vhd index 0127d1e2..31a61d0d 100755 --- a/hardware/jellybean/sgpio_if/top.vhd +++ b/hardware/jellybean/sgpio_if/top.vhd @@ -27,7 +27,6 @@ use UNISIM.vcomponents.all; entity top is Port( HOST_DATA : inout std_logic_vector(7 downto 0); - HOST_CLK : out std_logic; HOST_CAPTURE : out std_logic; HOST_DISABLE : in std_logic; HOST_DIRECTION : in std_logic; @@ -50,7 +49,6 @@ architecture Behavioral of top is signal dac_data_o : std_logic_vector(9 downto 0); signal host_clk_i : std_logic; - signal host_clk_o : std_logic; type transfer_direction is (from_adc, to_dac); signal transfer_direction_i : transfer_direction; @@ -90,7 +88,6 @@ begin else (others => 'Z'); data_from_host_i <= HOST_DATA; - HOST_CLK <= host_clk_o; HOST_CAPTURE <= host_data_capture_o; host_data_enable_i <= not HOST_DISABLE; transfer_direction_i <= to_dac when HOST_DIRECTION = '1' @@ -98,10 +95,6 @@ begin ------------------------------------------------ - host_clk_o <= host_clk_i; - - ------------------------------------------------ - process(host_clk_i) begin if rising_edge(host_clk_i) then diff --git a/hardware/jellybean/sgpio_if/top_tb.vhd b/hardware/jellybean/sgpio_if/top_tb.vhd index abd9dd92..3c15e9b2 100755 --- a/hardware/jellybean/sgpio_if/top_tb.vhd +++ b/hardware/jellybean/sgpio_if/top_tb.vhd @@ -29,7 +29,6 @@ ARCHITECTURE behavior OF top_tb IS COMPONENT top PORT( HOST_DATA : INOUT std_logic_vector(7 downto 0); - HOST_CLK : OUT std_logic; HOST_CAPTURE : OUT std_logic; HOST_DISABLE : IN std_logic; HOST_DIRECTION : IN std_logic; @@ -56,14 +55,12 @@ ARCHITECTURE behavior OF top_tb IS --Outputs signal DD : std_logic_vector(9 downto 0); - signal HOST_CLK : std_logic; signal HOST_CAPTURE : std_logic; begin uut: top PORT MAP ( HOST_DATA => HOST_DATA, - HOST_CLK => HOST_CLK, HOST_CAPTURE => HOST_CAPTURE, HOST_DISABLE => HOST_DISABLE, HOST_DIRECTION => HOST_DIRECTION, @@ -126,10 +123,10 @@ begin for i in 0 to 10 loop HOST_DATA <= (others => '0'); - wait until rising_edge(host_clk) and HOST_CAPTURE = '1'; + wait until rising_edge(CODEC_CLK) and HOST_CAPTURE = '1'; HOST_DATA <= (others => '1'); - wait until rising_edge(host_clk) and HOST_CAPTURE = '1'; + wait until rising_edge(CODEC_CLK) and HOST_CAPTURE = '1'; end loop; wait;