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Reworked sgpio.c to make use of #defines for fields, instead of hard-coding shifts. Proper.

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This commit is contained in:
Jared Boone
2012-10-11 20:46:21 -07:00
parent 9b579232a7
commit a1af4356b6
1 changed files with 63 additions and 36 deletions
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95
firmware/common/sgpio.c
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@ -59,17 +59,23 @@ void sgpio_test_interface() {
// Make all SGPIO controlled by SGPIO's "GPIO" registers // Make all SGPIO controlled by SGPIO's "GPIO" registers
for (uint_fast8_t i = 0; i < 16; i++) { for (uint_fast8_t i = 0; i < 16; i++) {
SGPIO_OUT_MUX_CFG(i) = (0L << 4) | (4L << 0); SGPIO_OUT_MUX_CFG(i) =
SGPIO_OUT_MUX_CFG_P_OE_CFG(0)
| SGPIO_OUT_MUX_CFG_P_OUT_CFG(4);
} }
// Set SGPIO output values. // Set SGPIO output values.
SGPIO_GPIO_OUTREG = (1L << host_direction_sgpio_pin) SGPIO_GPIO_OUTREG =
(1L << host_direction_sgpio_pin)
| (1L << host_disable_sgpio_pin); | (1L << host_disable_sgpio_pin);
// Enable SGPIO pin outputs. // Enable SGPIO pin outputs.
SGPIO_GPIO_OENREG = (1L << host_direction_sgpio_pin) SGPIO_GPIO_OENREG =
| (1L << host_disable_sgpio_pin) | (0L << host_capture_sgpio_pin) (1L << host_direction_sgpio_pin)
| (0L << host_clock_sgpio_pin) | (0xFF << 0); | (1L << host_disable_sgpio_pin)
| (0L << host_capture_sgpio_pin)
| (0L << host_clock_sgpio_pin)
| (0xFF << 0);
// Configure SGPIO slices. // Configure SGPIO slices.
@ -96,8 +102,9 @@ void sgpio_configure(
const uint_fast8_t cpld_direction = const uint_fast8_t cpld_direction =
(transceiver_mode == TRANSCEIVER_MODE_TX) ? 1 : 0; (transceiver_mode == TRANSCEIVER_MODE_TX) ? 1 : 0;
SGPIO_GPIO_OUTREG = SGPIO_GPIO_OUTREG =
(cpld_direction << 11) | // direction (cpld_direction << 11)
(1L << 10); // disable | (1L << 10) // disable
;
// Enable SGPIO pin outputs. // Enable SGPIO pin outputs.
const uint_fast16_t sgpio_gpio_data_direction = const uint_fast16_t sgpio_gpio_data_direction =
@ -105,24 +112,38 @@ void sgpio_configure(
? (0xFF << 0) ? (0xFF << 0)
: (0x00 << 0); : (0x00 << 0);
SGPIO_GPIO_OENREG = SGPIO_GPIO_OENREG =
(1L << 11) | // direction (1L << 11) // direction
(1L << 10) | // disable | (1L << 10) // disable
(0L << 9) | // capture | (0L << 9) // capture
(0L << 8) | // clock | (0L << 8) // clock
sgpio_gpio_data_direction; // data: output | sgpio_gpio_data_direction
;
SGPIO_OUT_MUX_CFG( 8) = 0; // SGPIO: Input: clock SGPIO_OUT_MUX_CFG( 8) = // SGPIO: Input: clock
SGPIO_OUT_MUX_CFG( 9) = 0; // SGPIO: Input: qualifier SGPIO_OUT_MUX_CFG_P_OE_CFG(0)
SGPIO_OUT_MUX_CFG(10) = (0L << 4) | (4L << 0); // GPIO: Output: disable | SGPIO_OUT_MUX_CFG_P_OUT_CFG(0)
SGPIO_OUT_MUX_CFG(11) = (0L << 4) | (4L << 0); // GPIO: Output: direction ;
SGPIO_OUT_MUX_CFG( 9) = // SGPIO: Input: qualifier
SGPIO_OUT_MUX_CFG_P_OE_CFG(0)
| SGPIO_OUT_MUX_CFG_P_OUT_CFG(0)
;
SGPIO_OUT_MUX_CFG(10) = // GPIO: Output: disable
SGPIO_OUT_MUX_CFG_P_OE_CFG(0)
| SGPIO_OUT_MUX_CFG_P_OUT_CFG(4)
;
SGPIO_OUT_MUX_CFG(11) = // GPIO: Output: direction
SGPIO_OUT_MUX_CFG_P_OE_CFG(0)
| SGPIO_OUT_MUX_CFG_P_OUT_CFG(4)
;
const uint_fast8_t output_multiplexing_mode = const uint_fast8_t output_multiplexing_mode =
multi_slice ? 11 : 9; multi_slice ? 11 : 9;
for(uint_fast8_t i=0; i<8; i++) { for(uint_fast8_t i=0; i<8; i++) {
// SGPIO pin 0 outputs slice A bit "i". // SGPIO pin 0 outputs slice A bit "i".
SGPIO_OUT_MUX_CFG(i) = SGPIO_OUT_MUX_CFG(i) =
(0L << 4) | // P_OE_CFG = 0 SGPIO_OUT_MUX_CFG_P_OE_CFG(0)
(output_multiplexing_mode << 0); | SGPIO_OUT_MUX_CFG_P_OUT_CFG(output_multiplexing_mode)
;
} }
const uint_fast8_t slice_indices[] = { const uint_fast8_t slice_indices[] = {
@ -146,28 +167,34 @@ void sgpio_configure(
const uint_fast8_t concat_order = (input_slice || single_slice) ? 0 : 3; const uint_fast8_t concat_order = (input_slice || single_slice) ? 0 : 3;
const uint_fast8_t concat_enable = (input_slice || single_slice) ? 0 : 1; const uint_fast8_t concat_enable = (input_slice || single_slice) ? 0 : 1;
const uint_fast8_t pos = multi_slice ? 0x1f : 0x03; const uint_fast8_t pos = multi_slice ? 0x1f : 0x03;
SGPIO_MUX_CFG(slice_index) = SGPIO_MUX_CFG(slice_index) =
(concat_order << 12) | SGPIO_MUX_CFG_CONCAT_ORDER(concat_order)
(concat_enable << 11) | | SGPIO_MUX_CFG_CONCAT_ENABLE(concat_enable)
(0L << 9) | // QUALIFIER_SLICE_MODE = X | SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE(0)
(1L << 7) | // QUALIFIER_PIN_MODE = 1 (SGPIO9) | SGPIO_MUX_CFG_QUALIFIER_PIN_MODE(1)
(3L << 5) | // QUALIFIER_MODE = 3 (external SGPIO pin) | SGPIO_MUX_CFG_QUALIFIER_MODE(3)
(0L << 3) | // CLK_SOURCE_SLICE_MODE = X | SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE(0)
(0L << 1) | // CLK_SOURCE_PIN_MODE = 0 (SGPIO8) | SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE(0)
(1L << 0); // EXT_CLK_ENABLE = 1, external clock signal (slice) | SGPIO_MUX_CFG_EXT_CLK_ENABLE(1)
;
SGPIO_SLICE_MUX_CFG(slice_index) = SGPIO_SLICE_MUX_CFG(slice_index) =
(0L << 8) | // INV_QUALIFIER = 0 (use normal qualifier) SGPIO_SLICE_MUX_CFG_INV_QUALIFIER(0)
(3L << 6) | // PARALLEL_MODE = 3 (shift 8 bits per clock) | SGPIO_SLICE_MUX_CFG_PARALLEL_MODE(3)
(0L << 4) | // DATA_CAPTURE_MODE = 0 (detect rising edge) | SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE(0)
(0L << 3) | // INV_OUT_CLK = X | SGPIO_SLICE_MUX_CFG_INV_OUT_CLK(0)
(1L << 2) | // CLKGEN_MODE = 1 (use external pin clock) | SGPIO_SLICE_MUX_CFG_CLKGEN_MODE(1)
(1L << 1) | // CLK_CAPTURE_MODE = 1 (use falling clock edge) | SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE(1)
(0L << 0); // MATCH_MODE = 0 (do not match data) | SGPIO_SLICE_MUX_CFG_MATCH_MODE(0)
;
SGPIO_PRESET(slice_index) = 0; // External clock, don't care SGPIO_PRESET(slice_index) = 0; // External clock, don't care
SGPIO_COUNT(slice_index) = 0; // External clock, don't care SGPIO_COUNT(slice_index) = 0; // External clock, don't care
SGPIO_POS(slice_index) = (pos << 8) | (pos << 0); SGPIO_POS(slice_index) =
SGPIO_POS_POS_RESET(pos)
| SGPIO_POS_POS(pos)
;
SGPIO_REG(slice_index) = 0x80808080; // Primary output data register SGPIO_REG(slice_index) = 0x80808080; // Primary output data register
SGPIO_REG_SS(slice_index) = 0x80808080; // Shadow output data register SGPIO_REG_SS(slice_index) = 0x80808080; // Shadow output data register