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Remove source for development firmwares

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This commit is contained in:
Dominic Spill
2017-02-14 21:08:45 -07:00
parent c6be7dea3e
commit 9e3b69a9b7
34 changed files with 0 additions and 3915 deletions
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32
firmware/mixertx/CMakeLists.txt
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# Copyright 2014 Jared Boone <jared@sharebrained.com>
#
# This file is part of HackRF.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
#
cmake_minimum_required(VERSION 2.8.9)
set(CMAKE_TOOLCHAIN_FILE ../toolchain-arm-cortex-m.cmake)
project(mixertx)
include(../hackrf-common.cmake)
set(SRC_M4
mixertx.c
)
DeclareTargets()

26
firmware/mixertx/README
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This program activates the MAX2837 transceiver to transmit an unmodulated
carrier. It also configures the RFFC5071 to downconvert the carrier to a lower
frequency.
Required Lemondrop -> Jellybean connections:
SCK: Lemondrop P3 pin 2 -> Jellybean P9 2
MOSI: Lemondrop P3 pin 4 -> Jellybean P9 4
MISO: Lemondrop P3 pin 6 -> Jellybean P9 6
SSEL: Lemondrop P3 pin 3 -> Jellybean P9 3
SCL: Lemondrop P7 pin 3 -> Jellybean P6 pin 3
SDA: Lemondrop P7 pin 5 -> Jellybean P6 pin 5
SDA: Lemondrop P7 pin 6 -> Jellybean P6 pin 6
VCC: Lemondrop P4 pin 2, 4, or 6 -> Jellybean P17 pin 2, 4, or 6
1V8: Lemondrop P11 pin 2, 4, or 6 -> Jellybean P16 pin 2, 4, or 6
GND: Lemondrop P5 -> Jellybean P13
Required Lollipop -> Jellybean connections:
GND: Lollipop P8 pin 1, 3, or 5 -> Jellybean P17 pin 1, 3, or 5
VCC: Lollipop P8 pin 2, 4, or 6 -> Jellybean P17 pin 2, 4, or 6
ENX: Lollipop P4 pin 5 -> Jellybean P5 pin 2
SCLK: Lollipop P4 pin 3 -> Jellybean P5 pin 4
SDATA: Lollipop P4 pin 1 -> Jellybean P5 pin 6
Also RF connectors, and you're on your own to get the RF switches configured
properly.

50
firmware/mixertx/mixertx.c
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/*
* Copyright 2012 Michael Ossmann
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#include "hackrf_core.h"
int main(void)
{
const uint32_t freq = 2441000000U;
pin_setup();
enable_1v8_power();
#ifdef HACKRF_ONE
enable_rf_power();
#endif
cpu_clock_init();
led_on(LED1);
ssp1_set_mode_max2837();
max2837_setup(&max2837);
mixer_setup(&mixer);
led_on(LED2);
max2837_set_frequency(&max2837, freq);
max2837_start(&max2837);
max2837_tx(&max2837);
led_on(LED3);
while (1);
max2837_stop(&max2837);
return 0;
}

33
firmware/sgpio-rx/CMakeLists.txt
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@ -1,33 +0,0 @@
# Copyright 2012 Jared Boone <jared@sharebrained.com>
#
# This file is part of HackRF.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
#
cmake_minimum_required(VERSION 2.8.9)
set(CMAKE_TOOLCHAIN_FILE ../toolchain-arm-cortex-m.cmake)
project(sgpio-rx)
include(../hackrf-common.cmake)
set(SRC_M4
sgpio-rx.c
${PATH_HACKRF_FIRMWARE_COMMON}/tuning.c
)
DeclareTargets()

1
firmware/sgpio-rx/README
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This is a variation of sgpio.c for testing RX.

101
firmware/sgpio-rx/sgpio-rx.c
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/*
* Copyright 2012 Michael Ossmann
* Copyright (C) 2012 Jared Boone
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#include <libopencm3/lpc43xx/sgpio.h>
#include <hackrf_core.h>
#include <tuning.h>
void tx_test() {
// LSB goes out first, samples are 0x<Q1><I1><Q0><I0>
volatile uint32_t buffer[] = {
0xda808080,
0xda80ff80,
0x26808080,
0x26800180,
};
uint32_t i = 0;
rf_path_set_direction(&rf_path, RF_PATH_DIRECTION_TX);
sgpio_cpld_stream_enable(&sgpio_config);
while(true) {
while(SGPIO_STATUS_1 == 0);
SGPIO_REG_SS(SGPIO_SLICE_A) = buffer[(i++) & 3];
SGPIO_CLR_STATUS_1 = 1;
}
}
void rx_test() {
volatile uint32_t buffer[4096];
uint32_t i = 0;
uint32_t magsq;
int8_t sigi, sigq;
rf_path_set_direction(&rf_path, RF_PATH_DIRECTION_RX);
sgpio_cpld_stream_enable(&sgpio_config);
led_on(LED2);
while(true) {
while(SGPIO_STATUS_1 == 0);
led_on(LED1);
SGPIO_CLR_STATUS_1 = 1;
buffer[i & 4095] = SGPIO_REG_SS(SGPIO_SLICE_A);
/* find the magnitude squared */
sigi = buffer[i & 4095] & 0xff;
sigq = (buffer[i & 4095] >> 8) & 0xff;
magsq = sigi * sigi + sigq * sigq;
/* illuminate LED3 only when magsq exceeds threshold */
if (magsq > 0x1000)
led_on(LED3);
else
led_off(LED3);
i++;
}
}
int main(void) {
const uint64_t freq = 2441000000U;
sgpio_set_slice_mode(&sgpio_config, false);
pin_setup();
enable_1v8_power();
#ifdef HACKRF_ONE
enable_rf_power();
#endif
cpu_clock_init();
rf_path_init(&rf_path);
set_freq(freq);
rx_test();
led_on(LED2);
while (1) {
}
return 0;
}

57
firmware/sgpio-rx/table.py
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mossmann@grumio ~/github/hackrf/firmware/simpletx $ python
Python 2.7.3 (default, Jun 22 2012, 11:10:47)
[GCC 4.5.3] on linux2
Type "help", "copyright", "credits" or "license" for more information.
>>> import math
>>> def y(i,max):
... return int(127.5*(math.sin(tau*i/max)+1))
...
>>> tau=math.pi*2
>>> def x(i,max):
... return int(127.5*(math.cos(tau*i/max)+1))
...
>>> def table(max):
... for i in range(0, max, 2):
... print "%02x%02x%02x%02x," % (y(i+1,max), x(i+1,max), y(i,max), x(i,max))
...
>>> table(32)
98fc7fff,
c6e9b0f5,
e9c6d9d9,
fc98f5b0,
fc66ff7f,
e938f54e,
c615d925,
9802b009,
66027f00,
38154e09,
15382525,
0266094e,
0298007f,
15c609b0,
38e925d9,
66fc4ef5,
>>> def table(max):
... for i in range(0, max, 2):
... print "0x%02x%02x%02x%02x," % (y(i+1,max), x(i+1,max), y(i,max), x(i,max))
...
>>> table(32)
0x98fc7fff,
0xc6e9b0f5,
0xe9c6d9d9,
0xfc98f5b0,
0xfc66ff7f,
0xe938f54e,
0xc615d925,
0x9802b009,
0x66027f00,
0x38154e09,
0x15382525,
0x0266094e,
0x0298007f,
0x15c609b0,
0x38e925d9,
0x66fc4ef5,

32
firmware/sgpio/CMakeLists.txt
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# Copyright 2012 Jared Boone <jared@sharebrained.com>
#
# This file is part of HackRF.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
#
cmake_minimum_required(VERSION 2.8.9)
set(CMAKE_TOOLCHAIN_FILE ../toolchain-arm-cortex-m.cmake)
project(sgpio_test)
include(../hackrf-common.cmake)
set(SRC_M4
sgpio_test.c
)
DeclareTargets()

2
firmware/sgpio/README
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A program to demonstrate TX control of the MAX5864 DAC, via the
SGPIO CPLD interface.

80
firmware/sgpio/sgpio_test.c
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/*
* Copyright 2012 Michael Ossmann
* Copyright (C) 2012 Jared Boone
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#include <libopencm3/lpc43xx/sgpio.h>
#include <hackrf_core.h>
volatile uint32_t buffer[4096];
void tx_test() {
sgpio_set_slice_mode(&sgpio_config, false);
sgpio_configure(&sgpio_config, TRANSCEIVER_MODE_TX);
// LSB goes out first, samples are 0x<Q1><I1><Q0><I0>
buffer[0] = 0xda808080;
buffer[1] = 0xda80ff80;
buffer[2] = 0x26808080;
buffer[3] = 0x26800180;
uint32_t i = 0;
sgpio_cpld_stream_enable(&sgpio_config);
while(true) {
while(SGPIO_STATUS_1 == 0);
SGPIO_REG_SS(SGPIO_SLICE_A) = buffer[(i++) & 3];
SGPIO_CLR_STATUS_1 = 1;
}
}
void rx_test() {
sgpio_set_slice_mode(&sgpio_config, false);
sgpio_configure(&sgpio_config, TRANSCEIVER_MODE_RX);
uint32_t i = 0;
sgpio_cpld_stream_enable(&sgpio_config);
while(true) {
while(SGPIO_STATUS_1 == 0);
SGPIO_CLR_STATUS_1 = 1;
buffer[i++ & 4095] = SGPIO_REG_SS(SGPIO_SLICE_A);
}
}
int main(void) {
pin_setup();
enable_1v8_power();
cpu_clock_init();
led_on(LED1);
ssp1_set_mode_max5864();
max5864_setup(&max5864);
max5864_xcvr(&max5864);
while (1) {
}
return 0;
}

33
firmware/sgpio_passthrough/CMakeLists.txt
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# Copyright 2012 Jared Boone <jared@sharebrained.com>
# Copyright 2012 Benjamin Vernoux <titanmkd@gmail.com>
#
# This file is part of HackRF.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
#
cmake_minimum_required(VERSION 2.8.9)
set(CMAKE_TOOLCHAIN_FILE ../toolchain-arm-cortex-m.cmake)
project(sgpio_passthrough)
include(../hackrf-common.cmake)
set(SRC_M4
sgpio_passthrough.c
)
DeclareTargets()

5
firmware/sgpio_passthrough/README
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A program to test SGPIO with CPLD passthrough Input & Output via the SGPIO CPLD interface (P8 BANK2_AUX).
For this test connect P10 BANK1_AUX AUX9 pin to +1V8 (in order to have P8 BANK2_AUX AUX1 to 16 as Output).
This test requires:
* JellyBean+Lemondrop(to set clock at 204MHz).
* CPLD X2C64A hardware\jellybean\sgpio_if_passthrough\sgpio_if_passthrough.svf to be loaded first.

BIN
firmware/sgpio_passthrough/Test_SGPIO0_to15.ods
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BIN
firmware/sgpio_passthrough/Test_SGPIO0_to15.pdf
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68
firmware/sgpio_passthrough/Test_SGPIO_GPIO_mode_test_sgpio_interface.txt
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Test SGPIO GPIO mode, with LPC4330@204MHz (JellyBean+Lemondrop) and code executed in RAM.
Test1:
------
while(1)
{
for (uint_fast8_t i = 0; i < 8; i++)
{
SGPIO_GPIO_OUTREG ^= (1L << i);
}
}
Oscilloscope result (on SGPIO0): Frequency 750KHz => 272 cycles
Test2:
------
while(1)
{
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
SGPIO_GPIO_OUTREG ^= 0x5555;
}
Oscilloscope result (on SGPIO0): 3.923 MHz => 52 cycles
Test3:
------
while(1)
{
SGPIO_GPIO_OUTREG ^= 0x5555;
}
Oscilloscope result (on SGPIO0): Frequency 7.28MHz => 28 cycles
Test4:
------
while(1)
{
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
SGPIO_GPIO_OUTREG = 0x5555;
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
SGPIO_GPIO_OUTREG = 0xAAAA;
}
Oscilloscope result (on SGPIO0): Frequency 17MHz => 12 cycles
Test5:
------
while(1)
{
SGPIO_GPIO_OUTREG = 0x5555;
SGPIO_GPIO_OUTREG = 0xAAAA;
}
Oscilloscope result (on SGPIO0): Frequency 25.5MHz => 8 cycles

362
firmware/sgpio_passthrough/sgpio_passthrough.c
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/*
* Copyright 2012 Michael Ossmann
* Copyright (C) 2012 Jared Boone
* Copyright (C) 2012 Benjamin Vernoux
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#include <libopencm3/lpc43xx/scu.h>
#include <libopencm3/lpc43xx/sgpio.h>
#include <hackrf_core.h>
void configure_sgpio_pin_functions() {
scu_pinmux(SCU_PINMUX_SGPIO0, SCU_GPIO_FAST | SCU_CONF_FUNCTION3);
scu_pinmux(SCU_PINMUX_SGPIO1, SCU_GPIO_FAST | SCU_CONF_FUNCTION3);
scu_pinmux(SCU_PINMUX_SGPIO2, SCU_GPIO_FAST | SCU_CONF_FUNCTION2);
scu_pinmux(SCU_PINMUX_SGPIO3, SCU_GPIO_FAST | SCU_CONF_FUNCTION2);
scu_pinmux(SCU_PINMUX_SGPIO4, SCU_GPIO_FAST | SCU_CONF_FUNCTION2);
scu_pinmux(SCU_PINMUX_SGPIO5, SCU_GPIO_FAST | SCU_CONF_FUNCTION2);
scu_pinmux(SCU_PINMUX_SGPIO6, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_PINMUX_SGPIO7, SCU_GPIO_FAST | SCU_CONF_FUNCTION6);
scu_pinmux(SCU_PINMUX_SGPIO8, SCU_GPIO_FAST | SCU_CONF_FUNCTION6);
scu_pinmux(SCU_PINMUX_SGPIO9, SCU_GPIO_FAST | SCU_CONF_FUNCTION7);
scu_pinmux(SCU_PINMUX_SGPIO10, SCU_GPIO_FAST | SCU_CONF_FUNCTION6);
scu_pinmux(SCU_PINMUX_SGPIO11, SCU_GPIO_FAST | SCU_CONF_FUNCTION6);
scu_pinmux(SCU_PINMUX_SGPIO12, SCU_GPIO_FAST | SCU_CONF_FUNCTION6);
scu_pinmux(SCU_PINMUX_SGPIO13, SCU_GPIO_FAST | SCU_CONF_FUNCTION7);
scu_pinmux(SCU_PINMUX_SGPIO14, SCU_GPIO_FAST | SCU_CONF_FUNCTION7);
scu_pinmux(SCU_PINMUX_SGPIO15, SCU_GPIO_FAST | SCU_CONF_FUNCTION7);
}
void test_sgpio_sliceA_D(void)
{
SGPIO_GPIO_OENREG = 0; // All inputs for the moment.
// Disable all counters during configuration
SGPIO_CTRL_ENABLE = 0;
// Configure pin functions.
configure_sgpio_pin_functions();
/****************************************************/
/* Enable SGPIO pin outputs. */
/****************************************************/
SGPIO_GPIO_OENREG =
0xFFFF; // data: output for SGPIO0 to SGPIO15
/*******************************************************************************/
/* SGPIO pin 0 outputs slice A bit 0. (see Table 212. Output pin multiplexing) */
/*******************************************************************************/
SGPIO_OUT_MUX_CFG(0) =
(0L << 4) | // P_OE_CFG = X
(0L << 0); // P_OUT_CFG = 0, dout_doutm1 (1-bit mode)
// SGPIO pin 12 outputs slice D bit 0. (see Table 212. Output pin multiplexing)
SGPIO_OUT_MUX_CFG(12) =
(0L << 4) | // P_OE_CFG = X
(0L << 0); // P_OUT_CFG = 0, dout_doutm1 (1-bit mode)
/****************************************************/
/* Slice A */
/****************************************************/
SGPIO_MUX_CFG(SGPIO_SLICE_A) =
(0L << 12) | // CONCAT_ORDER = 0 (self-loop)
(1L << 11) | // CONCAT_ENABLE = 1 (concatenate data)
(0L << 9) | // QUALIFIER_SLICE_MODE = X
(0L << 7) | // QUALIFIER_PIN_MODE = X
(0L << 5) | // QUALIFIER_MODE = 0 (enable)
(0L << 3) | // CLK_SOURCE_SLICE_MODE = 0, slice D
(0L << 1) | // CLK_SOURCE_PIN_MODE = X
(0L << 0); // EXT_CLK_ENABLE = 0, internal clock signal (slice)
SGPIO_SLICE_MUX_CFG(SGPIO_SLICE_A) =
(0L << 8) | // INV_QUALIFIER = 0 (use normal qualifier)
(0L << 6) | // PARALLEL_MODE = 0 (shift 1 bit per clock)
(0L << 4) | // DATA_CAPTURE_MODE = 0 (detect rising edge)
(0L << 3) | // INV_OUT_CLK = 0 (normal clock)
(0L << 2) | // CLKGEN_MODE = 0 (use clock from COUNTER)
(0L << 1) | // CLK_CAPTURE_MODE = 0 (use rising clock edge)
(0L << 0); // MATCH_MODE = 0 (do not match data)
SGPIO_PRESET(SGPIO_SLICE_A) = 1;
SGPIO_COUNT(SGPIO_SLICE_A) = 0;
SGPIO_POS(SGPIO_SLICE_A) = (0x1FL << 8) | (0x1FL << 0);
SGPIO_REG(SGPIO_SLICE_A) = 0xAAAAAAAA; // Primary output data register
SGPIO_REG_SS(SGPIO_SLICE_A) = 0xAAAAAAAA; // Shadow output data register
/****************************************************/
/* Slice D (clock for Slice A) */
/****************************************************/
SGPIO_MUX_CFG(SGPIO_SLICE_D) =
(0L << 12) | // CONCAT_ORDER = 0 (self-loop)
(1L << 11) | // CONCAT_ENABLE = 1 (concatenate data)
(0L << 9) | // QUALIFIER_SLICE_MODE = X
(0L << 7) | // QUALIFIER_PIN_MODE = X
(0L << 5) | // QUALIFIER_MODE = 0 (enable)
(0L << 3) | // CLK_SOURCE_SLICE_MODE = 0, slice D
(0L << 1) | // CLK_SOURCE_PIN_MODE = X
(0L << 0); // EXT_CLK_ENABLE = 0, internal clock signal (slice)
SGPIO_SLICE_MUX_CFG(SGPIO_SLICE_D) =
(0L << 8) | // INV_QUALIFIER = 0 (use normal qualifier)
(0L << 6) | // PARALLEL_MODE = 0 (shift 1 bit per clock)
(0L << 4) | // DATA_CAPTURE_MODE = 0 (detect rising edge)
(0L << 3) | // INV_OUT_CLK = 0 (normal clock)
(0L << 2) | // CLKGEN_MODE = 0 (use clock from COUNTER)
(0L << 1) | // CLK_CAPTURE_MODE = 0 (use rising clock edge)
(0L << 0); // MATCH_MODE = 0 (do not match data)
SGPIO_PRESET(SGPIO_SLICE_D) = 0;
SGPIO_COUNT(SGPIO_SLICE_D) = 0;
SGPIO_POS(SGPIO_SLICE_D) = (0x1FL << 8) | (0x1FL << 0);
SGPIO_REG(SGPIO_SLICE_D) = 0xAAAAAAAA; // Primary output data register
SGPIO_REG_SS(SGPIO_SLICE_D) = 0xAAAAAAAA; // Shadow output data register
/****************************************************/
/* Start SGPIO operation by enabling slice clocks. */
/****************************************************/
SGPIO_CTRL_ENABLE =
(1L << SGPIO_SLICE_D) | // Slice D
(1L << SGPIO_SLICE_A); // Slice A
// Start SGPIO operation by enabling slice clocks.
/*
Expected:
SGPIO12 = MCU Freq/2
SGPIO0 = SGPIO12/2 MHz= 51MHz (SliceD/2)
*/
}
/*******************************************************************************/
/* Output 1bit table (see Table 212. Output pin multiplexing) */
/* SGPIO pin 00 outputs slice A bit 0. */
/* SGPIO pin 01 outputs slice I bit 0. */
/* SGPIO pin 02 outputs slice E bit 0. */
/* SGPIO pin 03 outputs slice J bit 0. */
/* SGPIO pin 04 outputs slice C bit 0. */
/* SGPIO pin 05 outputs slice K bit 0. */
/* SGPIO pin 06 outputs slice F bit 0. */
/* SGPIO pin 07 outputs slice L bit 0. */
/* SGPIO pin 08 outputs slice B bit 0. */
/* SGPIO pin 09 outputs slice M bit 0. */
/* SGPIO pin 10 outputs slice G bit 0. */
/* SGPIO pin 11 outputs slice N bit 0. */
/* SGPIO pin 12 outputs slice D bit 0. */
/* SGPIO pin 13 outputs slice O bit 0. */
/* SGPIO pin 14 outputs slice H bit 0. */
/* SGPIO pin 15 outputs slice P bit 0. */
/*******************************************************************************/
const uint8_t slice_preset_tab[16] =
{
0, /* Idx00 = Slice A => SGPIO0 Freq Div by 1=0 */
8, /* Idx01 = Slice B => SGPIO8 Freq Div by 9=8 */
4, /* Idx02 = Slice C => SGPIO4 Freq Div by 5=4 */
12, /* Idx03 = Slice D => SGPIO12 Freq Div by 13=12 */
2, /* Idx04 = Slice E => SGPIO2 Freq Div by 3=2 */
6, /* Idx05 = Slice F => SGPIO6 Freq Div by 7=6 */
10, /* Idx06 = Slice G => SGPIO10 Freq Div by 11=10 */
14, /* Idx07 = Slice H => SGPIO14 Freq Div by 15=14 */
1, /* Idx08 = Slice I => SGPIO1 Freq Div by 2=1 */
3, /* Idx09 = Slice J => SGPIO3 Freq Div by 4=3 */
5, /* Idx10 = Slice K => SGPIO5 Freq Div by 6=5 */
7, /* Idx11 = Slice L => SGPIO7 Freq Div by 8=7 */
9, /* Idx12 = Slice M => SGPIO9 Freq Div by 10=9 */
11, /* Idx13 = Slice N => SGPIO11 Freq Div by 12=11 */
13, /* Idx14 = Slice O => SGPIO13 Freq Div by 14=13 */
15 /* Idx15 = Slice P => SGPIO15 Freq Div by 16=15 */
};
void test_sgpio_all_slices(void)
{
SGPIO_GPIO_OENREG = 0; // All inputs for the moment.
// Disable all counters during configuration
SGPIO_CTRL_ENABLE = 0;
// Configure pin functions.
configure_sgpio_pin_functions();
/****************************************************/
/* Enable SGPIO pin outputs. */
/****************************************************/
SGPIO_GPIO_OENREG =
0xFFFF; // data: output for SGPIO0 to SGPIO15
for(uint_fast8_t i=0; i<16; i++)
{
SGPIO_OUT_MUX_CFG(i) =
(0L << 4) | // P_OE_CFG = X
(0L << 0); // P_OUT_CFG = 0, dout_doutm1 (1-bit mode)
}
/****************************************************/
/* Slice A to P */
/****************************************************/
for(uint_fast8_t i=0; i<16; i++)
{
SGPIO_MUX_CFG(i) =
(0L << 12) | // CONCAT_ORDER = 0 (self-loop)
(1L << 11) | // CONCAT_ENABLE = 1 (concatenate data)
(0L << 9) | // QUALIFIER_SLICE_MODE = X
(0L << 7) | // QUALIFIER_PIN_MODE = X
(0L << 5) | // QUALIFIER_MODE = 0 (enable)
(0L << 3) | // CLK_SOURCE_SLICE_MODE = 0, slice D
(0L << 1) | // CLK_SOURCE_PIN_MODE = X
(0L << 0); // EXT_CLK_ENABLE = 0, internal clock signal (slice)
SGPIO_SLICE_MUX_CFG(i) =
(0L << 8) | // INV_QUALIFIER = 0 (use normal qualifier)
(0L << 6) | // PARALLEL_MODE = 0 (shift 1 bit per clock)
(0L << 4) | // DATA_CAPTURE_MODE = 0 (detect rising edge)
(0L << 3) | // INV_OUT_CLK = 0 (normal clock)
(0L << 2) | // CLKGEN_MODE = 0 (use clock from COUNTER)
(0L << 1) | // CLK_CAPTURE_MODE = 0 (use rising clock edge)
(0L << 0); // MATCH_MODE = 0 (do not match data)
SGPIO_PRESET(i) = slice_preset_tab[i];
SGPIO_COUNT(i) = 0;
SGPIO_POS(i) = (0x1FL << 8) | (0x1FL << 0);
SGPIO_REG(i) = 0xAAAAAAAA; // Primary output data register
SGPIO_REG_SS(i) = 0xAAAAAAAA; // Shadow output data register
}
/****************************************************/
/* Start SGPIO operation by enabling slice clocks. */
/****************************************************/
SGPIO_CTRL_ENABLE = 0xFFFF; /* Start all slices A to P */
/*
(1L << SGPIO_SLICE_D) | // Slice D
(1L << SGPIO_SLICE_A); // Slice A
// Start SGPIO operation by enabling slice clocks.
*/
/*
Expected:
MCU Freq MHz = 204
SGPIO Theorical Freq MHz
SGPIO00 = 102,00000
SGPIO01 = 51,00000
SGPIO02 = 34,00000
SGPIO03 = 25,50000
SGPIO04 = 20,40000
SGPIO05 = 17,00000
SGPIO06 = 14,57143
SGPIO07 = 12,75000
SGPIO08 = 11,33333
SGPIO09 = 10,20000
SGPIO10 = 9,27273
SGPIO11 = 8,50000
SGPIO12 = 7,84615
SGPIO13 = 7,28571
SGPIO14 = 6,80000
SGPIO15 = 6,37500
TitanMKD: I have problems with my boards and this test see document Test_SGPIO0_to15.ods / Test_SGPIO0_to15.pdf
*/
}
void test_sgpio_interface(void)
{
SGPIO_GPIO_OENREG = 0; // All inputs for the moment.
// Disable all counters during configuration
SGPIO_CTRL_ENABLE = 0;
configure_sgpio_pin_functions();
// Make all SGPIO controlled by SGPIO's "GPIO" registers
for (uint_fast8_t i = 0; i < 16; i++) {
SGPIO_OUT_MUX_CFG(i) = (0L << 4) | (4L << 0);
}
// Enable SGPIO pin outputs (SGPIO0 to 15).
SGPIO_GPIO_OENREG = 0xFFFF;
/* Set values for SGPIO0 to 15 */
while (1)
{
// 750KHz => 272 cycles
/*
for (uint_fast8_t i = 0; i < 8; i++) {
SGPIO_GPIO_OUTREG ^= (1L << i);
}
*/
// 3.923 MHz => 52 cycles
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
SGPIO_GPIO_OUTREG ^= 0x5555;
// 7.28 MHz => 28 cycles
/*
SGPIO_GPIO_OUTREG ^= 0x5555;
*/
// 17 MHz => 12 cycles
/*
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
SGPIO_GPIO_OUTREG = 0x5555;
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
SGPIO_GPIO_OUTREG = 0xAAAA;
*/
// 25.50 MHz => 8 cycles
/*
SGPIO_GPIO_OUTREG = 0x5555;
SGPIO_GPIO_OUTREG = 0xAAAA;
*/
}
/* TitanMKD: I have problems with my board with this test (see test_sgpio_all_slices()) */
}
int main(void)
{
pin_setup();
enable_1v8_power();
cpu_clock_init();
led_on(LED1);
//test_sgpio_sliceA_D();
test_sgpio_interface();
//test_sgpio_all_slices();
while(1);
return 0;
}

32
firmware/simpletx/CMakeLists.txt
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# Copyright 2014 Jared Boone <jared@sharebrained.com>
#
# This file is part of HackRF.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
#
cmake_minimum_required(VERSION 2.8.9)
set(CMAKE_TOOLCHAIN_FILE ../toolchain-arm-cortex-m.cmake)
project(simpletx)
include(../hackrf-common.cmake)
set(SRC_M4
simpletx.c
)
DeclareTargets()

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firmware/simpletx/README
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This program activates the MAX2837 transceiver to transmit an unmodulated
carrier.
Required Lemondrop -> Jellybean connections:
SCK: Lemondrop P3 pin 2 -> Jellybean P9 2
CS_XCVR: Lemondrop P3 pin 3 -> Jellybean P9 3
MOSI: Lemondrop P3 pin 4 -> Jellybean P9 4
CS_AD: Lemondrop P3 pin 5 -> Jellybean P9 5
MISO: Lemondrop P3 pin 6 -> Jellybean P9 6
ENABLE: Lemondrop P6 pin 12 -> Jellybean P7 pin 12
RXENABLE: Lemondrop P6 pin 13 -> Jellybean P7 pin 13
TXENABLE: Lemondrop P6 pin 15 -> Jellybean P7 pin 15
SCL: Lemondrop P7 pin 3 -> Jellybean P6 pin 3
SDA: Lemondrop P7 pin 5 -> Jellybean P6 pin 5
SDA: Lemondrop P7 pin 6 -> Jellybean P6 pin 6
VCC: Lemondrop P4 pin 2, 4, or 6 -> Jellybean P17 pin 2, 4, or 6
GND: Lemondrop P5 -> Jellybean P13
For now we are running everything at 3.3 V, but in the future we may also
require:
1V8: Lemondrop P11 pin 2, 4, or 6 -> Jellybean P16 pin 2, 4, or 6

48
firmware/simpletx/simpletx.c
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/*
* Copyright 2012 Michael Ossmann
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#include "hackrf_core.h"
int main(void)
{
const uint32_t freq = 2441000000U;
pin_setup();
enable_1v8_power();
#ifdef HACKRF_ONE
enable_rf_power();
#endif
cpu_clock_init();
led_on(LED1);
ssp1_set_mode_max2837();
max2837_setup(&max2837);
led_on(LED2);
max2837_set_frequency(&max2837, freq);
max2837_start(&max2837);
max2837_tx(&max2837);
led_on(LED3);
while (1);
max2837_stop(&max2837);
return 0;
}

34
firmware/spiflash/CMakeLists.txt
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# Copyright 2012 Michael Ossmann <mike@ossmann.com>
# Copyright 2012 Jared Boone <jared@sharebrained.com>
#
# This file is part of HackRF.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
#
cmake_minimum_required(VERSION 2.8.9)
set(CMAKE_TOOLCHAIN_FILE ../toolchain-arm-cortex-m.cmake)
project(spiflash)
include(../hackrf-common.cmake)
set(SRC_M4
spiflash.c
"${PATH_HACKRF_FIRMWARE_COMMON}/w25q80bv.c"
)
DeclareTargets()

1
firmware/spiflash/README
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@ -1 +0,0 @@
This is a test program for SPI flash programming.

56
firmware/spiflash/spiflash.c
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@ -1,56 +0,0 @@
/*
* Copyright 2010 - 2012 Michael Ossmann
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#include "hackrf_core.h"
int main(void)
{
int i;
uint8_t buf[515];
pin_setup();
enable_1v8_power();
cpu_clock_init();
/* program test data to SPI flash */
for (i = 0; i < 515; i++)
buf[i] = (i * 3) & 0xFF;
w25q80bv_setup(&w25q80bv);
w25q80bv_chip_erase(&w25q80bv);
w25q80bv_program(&w25q80bv, 790, 515, &buf[0]);
/* blink LED1 and LED3 */
while (1)
{
led_on(LED1);
led_on(LED3);
for (i = 0; i < 8000000; i++) /* Wait a bit. */
__asm__("nop");
led_off(LED1);
led_off(LED3);
for (i = 0; i < 8000000; i++) /* Wait a bit. */
__asm__("nop");
}
return 0;
}

32
firmware/startup/CMakeLists.txt
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@ -1,32 +0,0 @@
# Copyright 2014 Jared Boone <jared@sharebrained.com>
#
# This file is part of HackRF.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
#
cmake_minimum_required(VERSION 2.8.9)
set(CMAKE_TOOLCHAIN_FILE ../toolchain-arm-cortex-m.cmake)
project(startup)
include(../hackrf-common.cmake)
set(SRC_M4
startup.c
)
DeclareTargets()

11
firmware/startup/README
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@ -1,11 +0,0 @@
This program is an example of the startup sequence for HackRF (Jellybean with
Lemondrop attached). LED1, LED2, and LED3 are illuminated upon success.
Required Lemondrop -> Jellybean connections:
SCL: Lemondrop P7 pin 3 -> Jellybean P6 pin 3
SDA: Lemondrop P7 pin 5 -> Jellybean P6 pin 5
SDA: Lemondrop P7 pin 6 -> Jellybean P6 pin 6
VCC: Lemondrop P4 pin 2, 4, or 6 -> Jellybean P17 pin 2, 4, or 6
1V8: Lemondrop P11 pin 2, 4, or 6 -> Jellybean P16 pin 2, 4, or 6
GND: Lemondrop P5 -> Jellybean P13

62
firmware/startup/startup.c
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@ -1,62 +0,0 @@
/*
* Copyright 2010 - 2012 Michael Ossmann
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#include "hackrf_core.h"
int main(void)
{
uint32_t i;
pin_setup();
enable_1v8_power();
cpu_clock_init();
led_on(LED1);
led_on(LED2);
led_on(LED3);
while (1)
{
led_on(LED1);
for (i = 0; i < 2000000; i++) /* Wait a bit. */
__asm__("nop");
led_on(LED2);
for (i = 0; i < 2000000; i++) /* Wait a bit. */
__asm__("nop");
led_on(LED3);
for (i = 0; i < 2000000; i++) /* Wait a bit. */
__asm__("nop");
led_off(LED1);
led_off(LED2);
led_off(LED3);
for (i = 0; i < 2000000; i++) /* Wait a bit. */
__asm__("nop");
}
return 0;
}

32
firmware/startup_systick/CMakeLists.txt
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@ -1,32 +0,0 @@
# Copyright 2014 Jared Boone <jared@sharebrained.com>
#
# This file is part of HackRF.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
#
cmake_minimum_required(VERSION 2.8.9)
set(CMAKE_TOOLCHAIN_FILE ../toolchain-arm-cortex-m.cmake)
project(startup_systick)
include(../hackrf-common.cmake)
set(SRC_M4
startup_systick.c
)
DeclareTargets()

12
firmware/startup_systick/README
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@ -1,12 +0,0 @@
This program is an example of the startup sequence for HackRF (Jellybean with
Lemondrop attached).
LED1, LED2, and LED3 are blinking at exactly a frequency of 1Hz upon success.
Required Lemondrop -> Jellybean connections:
SCL: Lemondrop P7 pin 3 -> Jellybean P6 pin 3
SDA: Lemondrop P7 pin 5 -> Jellybean P6 pin 5
SDA: Lemondrop P7 pin 6 -> Jellybean P6 pin 6
VCC: Lemondrop P4 pin 2, 4, or 6 -> Jellybean P17 pin 2, 4, or 6
1V8: Lemondrop P11 pin 2, 4, or 6 -> Jellybean P16 pin 2, 4, or 6
GND: Lemondrop P5 -> Jellybean P13

159
firmware/startup_systick/startup_systick.c
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@ -1,159 +0,0 @@
/*
* Copyright 2012 Benjamin Vernoux
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#include <libopencm3/lpc43xx/m4/nvic.h>
#include <libopencm3/cm3/systick.h>
#include <libopencm3/cm3/scs.h>
#include "hackrf_core.h"
/* Global counter incremented by SysTick Interrupt each millisecond */
volatile uint32_t g_ulSysTickCount;
uint32_t g_NbCyclePerSecond;
void systick_setup(void)
{
uint32_t systick_reload_val;
g_ulSysTickCount = 0;
/* Disable IRQ globally */
__asm__("cpsid i");
/* Set processor Clock as Source Clock */
systick_set_clocksource(STK_CTRL_CLKSOURCE);
/* Get SysTick calibration value to obtain by default 1 tick = 10ms */
systick_reload_val = systick_get_calib();
/*
* Calibration seems wrong on LPC43xx(TBC) for default Freq it assume System Clock is 12MHz but it is 12*17=204MHz
* Fix the Calibration value bu multiplication by 17
*/
systick_reload_val = (systick_reload_val*17);
/* To obtain 1ms per tick just divide by 10 the 10ms base tick and set the reload */
systick_reload_val = systick_reload_val/10;
systick_set_reload(systick_reload_val);
systick_interrupt_enable();
/* Start counting. */
systick_counter_enable();
/* Set SysTick Priority to maximum */
nvic_set_priority(NVIC_SYSTICK_IRQ, 0xFF);
/* Enable IRQ globally */
__asm__("cpsie i");
}
void scs_dwt_cycle_counter_enabled(void)
{
SCS_DEMCR |= SCS_DEMCR_TRCENA;
SCS_DWT_CTRL |= SCS_DWT_CTRL_CYCCNTENA;
}
uint32_t sys_tick_get_time_ms(void)
{
return g_ulSysTickCount;
}
uint32_t sys_tick_delta_time_ms(uint32_t start, uint32_t end)
{
#define MAX_T_U32 ((2^32)-1)
uint32_t diff;
if(end > start)
{
diff=end-start;
}else
{
diff=MAX_T_U32-(start-end)+1;
}
return diff;
}
void sys_tick_wait_time_ms(uint32_t wait_ms)
{
uint32_t start, end;
uint32_t tickms;
start = sys_tick_get_time_ms();
do
{
end = sys_tick_get_time_ms();
tickms = sys_tick_delta_time_ms(start, end);
}while(tickms < wait_ms);
}
/* Called each 1ms/1000Hz by interrupt
1) Count the number of cycle per second.
2) Increment g_ulSysTickCount counter.
*/
void sys_tick_handler(void)
{
if(g_ulSysTickCount==0)
{
/* Clear Cycle Counter*/
SCS_DWT_CYCCNT = 0;
}else if(g_ulSysTickCount==1000)
{
/* Capture number of cycle elapsed during 1 second */
g_NbCyclePerSecond = SCS_DWT_CYCCNT;
}
g_ulSysTickCount++;
}
int main(void)
{
pin_setup();
enable_1v8_power();
cpu_clock_init();
scs_dwt_cycle_counter_enabled();
systick_setup();
led_on(LED1);
led_on(LED2);
led_on(LED3);
while (1)
{
led_on(LED1);
led_on(LED2);
led_on(LED3);
sys_tick_wait_time_ms(500);
led_off(LED1);
led_off(LED2);
led_off(LED3);
sys_tick_wait_time_ms(500);
}
return 0;
}

33
firmware/startup_systick_perfo/CMakeLists.txt
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@ -1,33 +0,0 @@
# Copyright 2014 Jared Boone <jared@sharebrained.com>
#
# This file is part of HackRF.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
#
cmake_minimum_required(VERSION 2.8.9)
set(CMAKE_TOOLCHAIN_FILE ../toolchain-arm-cortex-m.cmake)
project(startup_systick_perfo_SPIFI)
include(../hackrf-common.cmake)
set(SRC_M4
startup_systick.c
perf_mips.c
)
DeclareTargets()

20
firmware/startup_systick_perfo/README
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@ -1,20 +0,0 @@
This program is an example of the startup sequence for HackRF (Jellybean with
Lemondrop attached).
Test number of instruction per second (MIPS) slow blink ON 1s, OFF 1s
Then after 16s (the 16tests) it blink LED1/2/3 ON/OFF each 250ms.
This example compute the number of instructions per second executed called also MIPS (Millions of Instructions Per Second)
This example code run from SRAM so maximum performance expected is 204MIPS.
See result details in result_exec_from_SRAM.txt
This example code run from SPIFI (SPI Quad mode) and the tests check different loop size to compute the cache size used with SPIFI and estimated to less than 256Bytes (about 128 instructions in best case and in Thumb2).
See result_exec_from_SPIFI.txt for more details.
Required Lemondrop -> Jellybean connections:
SCL: Lemondrop P7 pin 3 -> Jellybean P6 pin 3
SDA: Lemondrop P7 pin 5 -> Jellybean P6 pin 5
SDA: Lemondrop P7 pin 6 -> Jellybean P6 pin 6
VCC: Lemondrop P4 pin 2, 4, or 6 -> Jellybean P17 pin 2, 4, or 6
1V8: Lemondrop P11 pin 2, 4, or 6 -> Jellybean P16 pin 2, 4, or 6
GND: Lemondrop P5 -> Jellybean P13

2217
firmware/startup_systick_perfo/perf_mips.c
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File diff suppressed because it is too large Load Diff

33
firmware/startup_systick_perfo/result_exec_from_SPIFI.txt
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@ -1,33 +0,0 @@
Frequency MCU Core M4 = 204MHz
"nb_inst_per_sec" 0x10000008
nb_inst_per_sec[0] 195609816 test_nb_instruction_per_sec_100_nop_asm();
nb_inst_per_sec[1] 195577462 test_nb_instruction_per_sec_105_nop_asm();
nb_inst_per_sec[2] 195525410 test_nb_instruction_per_sec_110_nop_asm();
nb_inst_per_sec[3] 35423508 test_nb_instruction_per_sec_115_nop_asm();
nb_inst_per_sec[4] 5058688 test_nb_instruction_per_sec_120_nop_asm();
nb_inst_per_sec[5] 5094868 test_nb_instruction_per_sec_150_nop_asm();
nb_inst_per_sec[6] 5162144 test_nb_instruction_per_sec_200_nop_asm();
nb_inst_per_sec[7] 5505696 test_nb_instruction_per_sec_1000_nop_asm();
nb_inst_per_sec[8] 195600420 test_nb_instruction_per_sec_100_nop_asm();
nb_inst_per_sec[9] 195578027 test_nb_instruction_per_sec_105_nop_asm();
nb_inst_per_sec[10] 195525882 test_nb_instruction_per_sec_110_nop_asm();
nb_inst_per_sec[11] 35422647 test_nb_instruction_per_sec_115_nop_asm();
nb_inst_per_sec[12] 5058688 test_nb_instruction_per_sec_120_nop_asm();
nb_inst_per_sec[13] 5094868 test_nb_instruction_per_sec_150_nop_asm();
nb_inst_per_sec[14] 5162144 test_nb_instruction_per_sec_200_nop_asm();
nb_inst_per_sec[15] 5505696 test_nb_instruction_per_sec_1000_nop_asm();
Real speed expected from SPIFI without cache (with lot of nop)
Oscilloscope Freq SPIFI SCK = 22.50MHz to 22.83MHz (in reality 22.67MHz => 204/9 => SPIFI_CLK connected to IDIVB & IDIVB default=9)
So worst case 22.50Mbits*4 = 90Mbits/s => 11.25MBytes/s with an overhead of about 50% due to SPIFI protocol addr ... => 5.625MB
1 nop = 2 bytes (THUMB 0x00 0xBF) => Max 5.625 Millions instruction per second
110 NOP is in fact 110 + 9 (including loop overhead)
119*2 = 238 bytes
115NOP + 9 => does not enter in cache !! (248bytes)
Internal Cache size is about 256Bytes maybe shared Code/Data.
SPIFI obtained min=5.05 MIPS, max=195.6 MIPS

22
firmware/startup_systick_perfo/result_exec_from_SRAM.txt
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Frequency MCU Core M4 = 204MHz
"nb_inst_per_sec" 0x10080008
nb_inst_per_sec[0] 202091544 test_nb_instruction_per_sec_100_nop_asm();
nb_inst_per_sec[1] 202172820 test_nb_instruction_per_sec_105_nop_asm();
nb_inst_per_sec[2] 202247988 test_nb_instruction_per_sec_110_nop_asm();
nb_inst_per_sec[3] 202317165 test_nb_instruction_per_sec_115_nop_asm();
nb_inst_per_sec[4] 202381696 test_nb_instruction_per_sec_120_nop_asm();
nb_inst_per_sec[5] 202680030 test_nb_instruction_per_sec_150_nop_asm();
nb_inst_per_sec[6] 202986160 test_nb_instruction_per_sec_200_nop_asm();
nb_inst_per_sec[7] 203760144 test_nb_instruction_per_sec_1000_nop_asm();
nb_inst_per_sec[8] 202091220 test_nb_instruction_per_sec_100_nop_asm();
nb_inst_per_sec[9] 202172820 test_nb_instruction_per_sec_105_nop_asm();
nb_inst_per_sec[10] 202247988 test_nb_instruction_per_sec_110_nop_asm();
nb_inst_per_sec[11] 202317165 test_nb_instruction_per_sec_115_nop_asm();
nb_inst_per_sec[12] 202381696 test_nb_instruction_per_sec_120_nop_asm();
nb_inst_per_sec[13] 202680030 test_nb_instruction_per_sec_150_nop_asm();
nb_inst_per_sec[14] 202986160 test_nb_instruction_per_sec_200_nop_asm();
nb_inst_per_sec[15] 203760144 test_nb_instruction_per_sec_1000_nop_asm();
SRAM execution, expected 204 MIPS best case obtained min=202 MIPS, max=203.7 MIPS

206
firmware/startup_systick_perfo/startup_systick.c
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@ -1,206 +0,0 @@
/*
* Copyright 2010 - 2012 Michael Ossmann
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#include <libopencm3/lpc43xx/m4/nvic.h>
#include <libopencm3/cm3/systick.h>
#include <libopencm3/cm3/scs.h>
#include "hackrf_core.h"
/* Global counter incremented by SysTick Interrupt each millisecond */
volatile uint32_t g_ulSysTickCount;
uint32_t g_NbCyclePerSecond;
void systick_setup(void)
{
uint32_t systick_reload_val;
g_ulSysTickCount = 0;
/* Disable IRQ globally */
__asm__("cpsid i");
/* Set processor Clock as Source Clock */
systick_set_clocksource(STK_CTRL_CLKSOURCE);
/* Get SysTick calibration value to obtain by default 1 tick = 10ms */
systick_reload_val = systick_get_calib();
/*
* Calibration seems wrong on LPC43xx(TBC) for default Freq it assume System Clock is 12MHz but it is 12*17=204MHz
* Fix the Calibration value bu multiplication by 17
*/
systick_reload_val = (systick_reload_val*17);
/* To obtain 1ms per tick just divide by 10 the 10ms base tick and set the reload */
systick_reload_val = systick_reload_val/10;
systick_set_reload(systick_reload_val);
systick_interrupt_enable();
/* Start counting. */
systick_counter_enable();
/* Set SysTick Priority to maximum */
nvic_set_priority(NVIC_SYSTICK_IRQ, 0xFF);
/* Enable IRQ globally */
__asm__("cpsie i");
}
void scs_dwt_cycle_counter_enabled(void)
{
SCS_DEMCR |= SCS_DEMCR_TRCENA;
SCS_DWT_CTRL |= SCS_DWT_CTRL_CYCCNTENA;
}
uint32_t sys_tick_get_time_ms(void)
{
return g_ulSysTickCount;
}
uint32_t sys_tick_delta_time_ms(uint32_t start, uint32_t end)
{
#define MAX_T_U32 ((2^32)-1)
uint32_t diff;
if(end > start)
{
diff=end-start;
}else
{
diff=MAX_T_U32-(start-end)+1;
}
return diff;
}
void sys_tick_wait_time_ms(uint32_t wait_ms)
{
uint32_t start, end;
uint32_t tickms;
start = sys_tick_get_time_ms();
do
{
end = sys_tick_get_time_ms();
tickms = sys_tick_delta_time_ms(start, end);
}while(tickms < wait_ms);
}
/* Called each 1ms/1000Hz by interrupt
1) Count the number of cycle per second.
2) Increment g_ulSysTickCount counter.
*/
void sys_tick_handler(void)
{
if(g_ulSysTickCount==0)
{
/* Clear Cycle Counter*/
SCS_DWT_CYCCNT = 0;
}else if(g_ulSysTickCount==1000)
{
/* Capture number of cycle elapsed during 1 second */
g_NbCyclePerSecond = SCS_DWT_CYCCNT;
}
g_ulSysTickCount++;
}
uint32_t nb_inst_per_sec[16];
extern uint32_t test_nb_instruction_per_sec_100_nop_asm();
extern uint32_t test_nb_instruction_per_sec_105_nop_asm();
extern uint32_t test_nb_instruction_per_sec_110_nop_asm();
extern uint32_t test_nb_instruction_per_sec_115_nop_asm();
extern uint32_t test_nb_instruction_per_sec_120_nop_asm();
extern uint32_t test_nb_instruction_per_sec_150_nop_asm();
extern uint32_t test_nb_instruction_per_sec_200_nop_asm();
extern uint32_t test_nb_instruction_per_sec_1000_nop_asm();
#define LED1_TOGGLE() (led_toggle(LED1))
int main(void)
{
pin_setup();
enable_1v8_power();
cpu_clock_init();
scs_dwt_cycle_counter_enabled();
systick_setup();
led_off(LED1);
/* Test number of instruction per second (MIPS) slow blink ON 1s, OFF 1s */
LED1_TOGGLE();
nb_inst_per_sec[0] = test_nb_instruction_per_sec_100_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[1]= test_nb_instruction_per_sec_105_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[2]= test_nb_instruction_per_sec_110_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[3]= test_nb_instruction_per_sec_115_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[4] = test_nb_instruction_per_sec_120_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[5] = test_nb_instruction_per_sec_150_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[6] = test_nb_instruction_per_sec_200_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[7] = test_nb_instruction_per_sec_1000_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[8] = test_nb_instruction_per_sec_100_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[9]= test_nb_instruction_per_sec_105_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[10]= test_nb_instruction_per_sec_110_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[11]= test_nb_instruction_per_sec_115_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[12] = test_nb_instruction_per_sec_120_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[13] = test_nb_instruction_per_sec_150_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[14] = test_nb_instruction_per_sec_200_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[15] = test_nb_instruction_per_sec_1000_nop_asm();
LED1_TOGGLE();
/* Test finished fast blink */
while (1)
{
led_on(LED1);
led_on(LED2);
led_on(LED3);
sys_tick_wait_time_ms(250);
led_off(LED1);
led_off(LED2);
led_off(LED3);
sys_tick_wait_time_ms(250);
}
return 0;
}