From 9a7219eb4dbfed362be4ac0b7cb969caebd2059a Mon Sep 17 00:00:00 2001 From: Michael Ossmann Date: Thu, 7 Jun 2012 13:40:59 -0600 Subject: [PATCH] removed PLL1 stages as they no longer seem to be necessary since the power-down fix --- firmware/common/hackrf_core.c | 38 +++++++++-------------------------- 1 file changed, 9 insertions(+), 29 deletions(-) diff --git a/firmware/common/hackrf_core.c b/firmware/common/hackrf_core.c index d4453c35..c812c587 100644 --- a/firmware/common/hackrf_core.c +++ b/firmware/common/hackrf_core.c @@ -91,36 +91,8 @@ void cpu_clock_init(void) CGU_PLL1_CTRL = (CGU_PLL1_CTRL_AUTOBLOCK | (CGU_SRC_XTAL << CGU_PLL1_CTRL_CLK_SEL_SHIFT)); - /* configure PLL1 to produce 12 MHz clock from 12 MHz XTAL_OSC */ - CGU_PLL1_CTRL |= (CGU_PLL1_CTRL_FBSEL - | (3 << CGU_PLL1_CTRL_PSEL_SHIFT) - | (0 << CGU_PLL1_CTRL_NSEL_SHIFT) - | (0 << CGU_PLL1_CTRL_MSEL_SHIFT)); - - /* power on PLL1 and wait until stable */ - CGU_PLL1_CTRL &= ~CGU_PLL1_CTRL_PD; - while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK)); - - /* configure PLL1 to produce 108 MHz clock from 12 MHz XTAL_OSC */ - CGU_PLL1_CTRL &= ~(CGU_PLL1_CTRL_BYPASS - | CGU_PLL1_CTRL_FBSEL - | CGU_PLL1_CTRL_DIRECT - | CGU_PLL1_CTRL_DIRECT - | (0x3 << CGU_PLL1_CTRL_PSEL_SHIFT) - | (0x3 << CGU_PLL1_CTRL_NSEL_SHIFT) - | (0xFF << CGU_PLL1_CTRL_MSEL_SHIFT)); - CGU_PLL1_CTRL |= (CGU_PLL1_CTRL_FBSEL - | CGU_PLL1_CTRL_DIRECT - | (0 << CGU_PLL1_CTRL_PSEL_SHIFT) - | (0 << CGU_PLL1_CTRL_NSEL_SHIFT) - | (8 << CGU_PLL1_CTRL_MSEL_SHIFT)); - - /* use PLL1 as clock source for BASE_M4_CLK (CPU) */ - CGU_BASE_M4_CLK = (CGU_BASE_CLK_AUTOBLOCK - | (CGU_SRC_PLL1 << CGU_BASE_CLK_SEL_SHIFT)); - delay(1000000); - /* configure PLL1 to produce 204 MHz clock from 12 MHz XTAL_OSC */ + /* not sure why, but it doesn't work without the following line */ CGU_PLL1_CTRL &= ~(CGU_PLL1_CTRL_BYPASS | CGU_PLL1_CTRL_FBSEL | CGU_PLL1_CTRL_DIRECT @@ -133,6 +105,14 @@ void cpu_clock_init(void) | (0 << CGU_PLL1_CTRL_PSEL_SHIFT) | (0 << CGU_PLL1_CTRL_NSEL_SHIFT) | (16 << CGU_PLL1_CTRL_MSEL_SHIFT)); + + /* power on PLL1 and wait until stable */ + CGU_PLL1_CTRL &= ~CGU_PLL1_CTRL_PD; + while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK)); + + /* use PLL1 as clock source for BASE_M4_CLK (CPU) */ + CGU_BASE_M4_CLK = (CGU_BASE_CLK_AUTOBLOCK + | (CGU_SRC_PLL1 << CGU_BASE_CLK_SEL_SHIFT)); delay(1000000); /* use XTAL_OSC as clock source for PLL0USB */