From 9a66cefc812ddd0141038b9df9a59eae8c72a8fa Mon Sep 17 00:00:00 2001
From: Jared Boone <jboone@earfeast.com>
Date: Wed, 16 Jan 2019 18:06:01 -0800
Subject: [PATCH] CPLD: Set default IOSTANDARD to LVCMOS33, remove from UCF.

---
 firmware/cpld/sgpio_if/sgpio_if.xise |  2 +-
 firmware/cpld/sgpio_if/top.ucf       | 70 ++++++++++++++--------------
 2 files changed, 36 insertions(+), 36 deletions(-)

diff --git a/firmware/cpld/sgpio_if/sgpio_if.xise b/firmware/cpld/sgpio_if/sgpio_if.xise
index 4a238dc8..538bd875 100755
--- a/firmware/cpld/sgpio_if/sgpio_if.xise
+++ b/firmware/cpld/sgpio_if/sgpio_if.xise
@@ -80,7 +80,7 @@
     <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
     <property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
     <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
-    <property xil_pn:name="I/O Voltage Standard" xil_pn:value="LVCMOS18" xil_pn:valueState="default"/>
+    <property xil_pn:name="I/O Voltage Standard" xil_pn:value="LVCMOS33" xil_pn:valueState="non-default"/>
     <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="default"/>
     <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|top|Behavioral" xil_pn:valueState="non-default"/>
diff --git a/firmware/cpld/sgpio_if/top.ucf b/firmware/cpld/sgpio_if/top.ucf
index 58d77277..2104db81 100755
--- a/firmware/cpld/sgpio_if/top.ucf
+++ b/firmware/cpld/sgpio_if/top.ucf
@@ -29,41 +29,41 @@ TIMEGRP "to_host" OFFSET = OUT 20 ns AFTER "CODEC_X2_CLK";
 #PACE: Start of Constraints generated by PACE
 
 #PACE: Start of PACE I/O Pin Assignments
-NET "CODEC_CLK"  LOC = "P23" | IOSTANDARD = LVCMOS33 ; 
-NET "CODEC_X2_CLK"  LOC = "P27" | IOSTANDARD = LVCMOS33 ; 
-NET "DA<0>"  LOC = "P43" | IOSTANDARD = LVCMOS33 ; 
-NET "DA<1>"  LOC = "P42" | IOSTANDARD = LVCMOS33 ; 
-NET "DA<2>"  LOC = "P41" | IOSTANDARD = LVCMOS33 ; 
-NET "DA<3>"  LOC = "P40" | IOSTANDARD = LVCMOS33 ; 
-NET "DA<4>"  LOC = "P39" | IOSTANDARD = LVCMOS33 ; 
-NET "DA<5>"  LOC = "P37" | IOSTANDARD = LVCMOS33 ; 
-NET "DA<6>"  LOC = "P36" | IOSTANDARD = LVCMOS33 ; 
-NET "DA<7>"  LOC = "P35" | IOSTANDARD = LVCMOS33 ; 
-NET "DD<0>"  LOC = "P34" | IOSTANDARD = LVCMOS33  | SLEW = SLOW ; 
-NET "DD<1>"  LOC = "P33" | IOSTANDARD = LVCMOS33  | SLEW = SLOW ; 
-NET "DD<2>"  LOC = "P32" | IOSTANDARD = LVCMOS33  | SLEW = SLOW ; 
-NET "DD<3>"  LOC = "P30" | IOSTANDARD = LVCMOS33  | SLEW = SLOW ; 
-NET "DD<4>"  LOC = "P29" | IOSTANDARD = LVCMOS33  | SLEW = SLOW ; 
-NET "DD<5>"  LOC = "P28" | IOSTANDARD = LVCMOS33  | SLEW = SLOW ; 
-NET "DD<6>"  LOC = "P24" | IOSTANDARD = LVCMOS33  | SLEW = SLOW ; 
-NET "DD<7>"  LOC = "P19" | IOSTANDARD = LVCMOS33  | SLEW = SLOW ; 
-NET "DD<8>"  LOC = "P18" | IOSTANDARD = LVCMOS33  | SLEW = SLOW ; 
-NET "DD<9>"  LOC = "P17" | IOSTANDARD = LVCMOS33  | SLEW = SLOW ; 
-NET "HOST_CAPTURE"  LOC = "P91" | IOSTANDARD = LVCMOS33  | SLEW = SLOW ; 
-NET "HOST_DATA<0>"  LOC = "P89" | IOSTANDARD = LVCMOS33  | SLEW = SLOW ; 
-NET "HOST_DATA<1>"  LOC = "P79" | IOSTANDARD = LVCMOS33  | SLEW = SLOW ; 
-NET "HOST_DATA<2>"  LOC = "P74" | IOSTANDARD = LVCMOS33  | SLEW = SLOW ; 
-NET "HOST_DATA<3>"  LOC = "P72" | IOSTANDARD = LVCMOS33  | SLEW = SLOW ; 
-NET "HOST_DATA<4>"  LOC = "P67" | IOSTANDARD = LVCMOS33  | SLEW = SLOW ; 
-NET "HOST_DATA<5>"  LOC = "P64" | IOSTANDARD = LVCMOS33  | SLEW = SLOW ; 
-NET "HOST_DATA<6>"  LOC = "P61" | IOSTANDARD = LVCMOS33  | SLEW = SLOW ; 
-NET "HOST_DATA<7>"  LOC = "P77" | IOSTANDARD = LVCMOS33  | SLEW = SLOW ; 
-NET "HOST_DIRECTION"  LOC = "P71" | IOSTANDARD = LVCMOS33 ; 
-NET "HOST_DISABLE"  LOC = "P76" | IOSTANDARD = LVCMOS33 ; 
-NET "HOST_Q_INVERT"  LOC = "P70" | IOSTANDARD = LVCMOS33 ;
-NET "HOST_SYNC_EN" LOC = "P90" | IOSTANDARD = LVCMOS33 ; 
-NET "HOST_SYNC"  LOC = "P55" | IOSTANDARD = LVCMOS33 | PULLUP ; 
-NET "HOST_SYNC_CMD"  LOC = "P56" | IOSTANDARD = LVCMOS33  | SLEW = SLOW ; 
+NET "CODEC_CLK"  LOC = "P23" ; 
+NET "CODEC_X2_CLK"  LOC = "P27" ; 
+NET "DA<0>"  LOC = "P43" ; 
+NET "DA<1>"  LOC = "P42" ; 
+NET "DA<2>"  LOC = "P41" ; 
+NET "DA<3>"  LOC = "P40" ; 
+NET "DA<4>"  LOC = "P39" ; 
+NET "DA<5>"  LOC = "P37" ; 
+NET "DA<6>"  LOC = "P36" ; 
+NET "DA<7>"  LOC = "P35" ; 
+NET "DD<0>"  LOC = "P34" | SLEW = SLOW ; 
+NET "DD<1>"  LOC = "P33" | SLEW = SLOW ; 
+NET "DD<2>"  LOC = "P32" | SLEW = SLOW ; 
+NET "DD<3>"  LOC = "P30" | SLEW = SLOW ; 
+NET "DD<4>"  LOC = "P29" | SLEW = SLOW ; 
+NET "DD<5>"  LOC = "P28" | SLEW = SLOW ; 
+NET "DD<6>"  LOC = "P24" | SLEW = SLOW ; 
+NET "DD<7>"  LOC = "P19" | SLEW = SLOW ; 
+NET "DD<8>"  LOC = "P18" | SLEW = SLOW ; 
+NET "DD<9>"  LOC = "P17" | SLEW = SLOW ; 
+NET "HOST_CAPTURE"  LOC = "P91" | SLEW = SLOW ; 
+NET "HOST_DATA<0>"  LOC = "P89" | SLEW = SLOW ; 
+NET "HOST_DATA<1>"  LOC = "P79" | SLEW = SLOW ; 
+NET "HOST_DATA<2>"  LOC = "P74" | SLEW = SLOW ; 
+NET "HOST_DATA<3>"  LOC = "P72" | SLEW = SLOW ; 
+NET "HOST_DATA<4>"  LOC = "P67" | SLEW = SLOW ; 
+NET "HOST_DATA<5>"  LOC = "P64" | SLEW = SLOW ; 
+NET "HOST_DATA<6>"  LOC = "P61" | SLEW = SLOW ; 
+NET "HOST_DATA<7>"  LOC = "P77" | SLEW = SLOW ; 
+NET "HOST_DIRECTION"  LOC = "P71" ; 
+NET "HOST_DISABLE"  LOC = "P76" ; 
+NET "HOST_Q_INVERT"  LOC = "P70" ;
+NET "HOST_SYNC_EN" LOC = "P90" ; 
+NET "HOST_SYNC"  LOC = "P55" | PULLUP ; 
+NET "HOST_SYNC_CMD"  LOC = "P56"  | SLEW = SLOW ; 
 
 #PACE: Start of PACE Area Constraints