From 98b6e92f97e7e99c272452dd2880ca9c8dfa32aa Mon Sep 17 00:00:00 2001 From: Michael Ossmann Date: Thu, 7 Jun 2012 13:28:47 -0600 Subject: [PATCH] fixed PLL1 startup problem by not powering it down first --- firmware/common/hackrf_core.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/firmware/common/hackrf_core.c b/firmware/common/hackrf_core.c index e450290b..d4453c35 100644 --- a/firmware/common/hackrf_core.c +++ b/firmware/common/hackrf_core.c @@ -88,17 +88,14 @@ void cpu_clock_init(void) | (CGU_SRC_XTAL << CGU_BASE_CLK_SEL_SHIFT)); /* use XTAL_OSC as clock source for PLL1 */ - CGU_PLL1_CTRL = (CGU_PLL1_CTRL_PD - | CGU_PLL1_CTRL_AUTOBLOCK + CGU_PLL1_CTRL = (CGU_PLL1_CTRL_AUTOBLOCK | (CGU_SRC_XTAL << CGU_PLL1_CTRL_CLK_SEL_SHIFT)); - while (CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK); /* configure PLL1 to produce 12 MHz clock from 12 MHz XTAL_OSC */ CGU_PLL1_CTRL |= (CGU_PLL1_CTRL_FBSEL | (3 << CGU_PLL1_CTRL_PSEL_SHIFT) | (0 << CGU_PLL1_CTRL_NSEL_SHIFT) | (0 << CGU_PLL1_CTRL_MSEL_SHIFT)); - //FIXME why can't we get past this point? /* power on PLL1 and wait until stable */ CGU_PLL1_CTRL &= ~CGU_PLL1_CTRL_PD;