diff --git a/firmware/common/hackrf_core.c b/firmware/common/hackrf_core.c
index 9c3681e6..dc2f2013 100644
--- a/firmware/common/hackrf_core.c
+++ b/firmware/common/hackrf_core.c
@@ -327,55 +327,55 @@ void cpu_clock_init(void)
 #endif
 
 	/* set xtal oscillator to low frequency mode */
-	CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_HF;
+	CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_HF_MASK;
 
 	/* power on the oscillator and wait until stable */
-	CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_ENABLE;
+	CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_ENABLE_MASK;
 
 	/* Wait about 100us after Crystal Power ON */
 	delay(WAIT_CPU_CLOCK_INIT_DELAY);
 
 	/* use XTAL_OSC as clock source for BASE_M4_CLK (CPU) */
-	CGU_BASE_M4_CLK = (CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_XTAL) | CGU_BASE_M4_CLK_AUTOBLOCK);
+	CGU_BASE_M4_CLK = (CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_XTAL) | CGU_BASE_M4_CLK_AUTOBLOCK(1));
 
 	/* use XTAL_OSC as clock source for APB1 */
-	CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK
+	CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK(1)
 			| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_XTAL);
 
 	cpu_clock_pll1_low_speed();
 
 	/* use PLL1 as clock source for BASE_M4_CLK (CPU) */
-	CGU_BASE_M4_CLK = (CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_PLL1) | CGU_BASE_M4_CLK_AUTOBLOCK);
+	CGU_BASE_M4_CLK = (CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_PLL1) | CGU_BASE_M4_CLK_AUTOBLOCK(1));
 
 	/* use XTAL_OSC as clock source for PLL0USB */
-	CGU_PLL0USB_CTRL = CGU_PLL0USB_CTRL_PD
-			| CGU_PLL0USB_CTRL_AUTOBLOCK
+	CGU_PLL0USB_CTRL = CGU_PLL0USB_CTRL_PD(1)
+			| CGU_PLL0USB_CTRL_AUTOBLOCK(1)
 			| CGU_PLL0USB_CTRL_CLK_SEL(CGU_SRC_XTAL);
-	while (CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK);
+	while (CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK_MASK);
 
 	/* configure PLL0USB to produce 480 MHz clock from 12 MHz XTAL_OSC */
 	/* Values from User Manual v1.4 Table 94, for 12MHz oscillator. */
 	CGU_PLL0USB_MDIV = 0x06167FFA;
 	CGU_PLL0USB_NP_DIV = 0x00302062;
-	CGU_PLL0USB_CTRL |= (CGU_PLL0USB_CTRL_PD
-			| CGU_PLL0USB_CTRL_DIRECTI
-			| CGU_PLL0USB_CTRL_DIRECTO
-			| CGU_PLL0USB_CTRL_CLKEN);
+	CGU_PLL0USB_CTRL |= (CGU_PLL0USB_CTRL_PD(1)
+			| CGU_PLL0USB_CTRL_DIRECTI(1)
+			| CGU_PLL0USB_CTRL_DIRECTO(1)
+			| CGU_PLL0USB_CTRL_CLKEN(1));
 
 	/* power on PLL0USB and wait until stable */
-	CGU_PLL0USB_CTRL &= ~CGU_PLL0USB_CTRL_PD;
-	while (!(CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK));
+	CGU_PLL0USB_CTRL &= ~CGU_PLL0USB_CTRL_PD_MASK;
+	while (!(CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK_MASK));
 
 	/* use PLL0USB as clock source for USB0 */
-	CGU_BASE_USB0_CLK = CGU_BASE_USB0_CLK_AUTOBLOCK
+	CGU_BASE_USB0_CLK = CGU_BASE_USB0_CLK_AUTOBLOCK(1)
 			| CGU_BASE_USB0_CLK_CLK_SEL(CGU_SRC_PLL0USB);
 
 	/* Switch peripheral clock over to use PLL1 (204MHz) */
-	CGU_BASE_PERIPH_CLK = CGU_BASE_PERIPH_CLK_AUTOBLOCK
+	CGU_BASE_PERIPH_CLK = CGU_BASE_PERIPH_CLK_AUTOBLOCK(1)
 			| CGU_BASE_PERIPH_CLK_CLK_SEL(CGU_SRC_PLL1);
 
 	/* Switch APB1 clock over to use PLL1 (204MHz) */
-	CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK
+	CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK(1)
 			| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_PLL1);
 }
 
@@ -397,20 +397,20 @@ void cpu_clock_pll1_low_speed(void)
 	*/
 	pll_reg = CGU_PLL1_CTRL;
 	/* Clear PLL1 bits */
-	pll_reg &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK | CGU_PLL1_CTRL_PD | CGU_PLL1_CTRL_FBSEL |  /* CLK SEL, PowerDown , FBSEL */
-				  CGU_PLL1_CTRL_BYPASS | /* BYPASS */
-				  CGU_PLL1_CTRL_DIRECT | /* DIRECT */
+	pll_reg &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK | CGU_PLL1_CTRL_PD_MASK | CGU_PLL1_CTRL_FBSEL_MASK |  /* CLK SEL, PowerDown , FBSEL */
+				  CGU_PLL1_CTRL_BYPASS_MASK | /* BYPASS */
+				  CGU_PLL1_CTRL_DIRECT_MASK | /* DIRECT */
 				  CGU_PLL1_CTRL_PSEL_MASK | CGU_PLL1_CTRL_MSEL_MASK | CGU_PLL1_CTRL_NSEL_MASK ); /* PSEL, MSEL, NSEL- divider ratios */
 	/* Set PLL1 up to 12MHz * 4 = 48MHz. */
 	pll_reg |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL)
 				| CGU_PLL1_CTRL_PSEL(0)
 				| CGU_PLL1_CTRL_NSEL(0)
 				| CGU_PLL1_CTRL_MSEL(3)
-				| CGU_PLL1_CTRL_FBSEL
-				| CGU_PLL1_CTRL_DIRECT;
+				| CGU_PLL1_CTRL_FBSEL(1)
+				| CGU_PLL1_CTRL_DIRECT(1);
 	CGU_PLL1_CTRL = pll_reg;
 	/* wait until stable */
-	while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK));
+	while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK_MASK));
 
 	/* Wait a delay after switch to new frequency with Direct mode */
 	delay(WAIT_CPU_CLOCK_INIT_DELAY);
@@ -432,19 +432,19 @@ void cpu_clock_pll1_max_speed(void)
 	*/
 	pll_reg = CGU_PLL1_CTRL;
 	/* Clear PLL1 bits */
-	pll_reg &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK | CGU_PLL1_CTRL_PD | CGU_PLL1_CTRL_FBSEL |  /* CLK SEL, PowerDown , FBSEL */
-				  CGU_PLL1_CTRL_BYPASS | /* BYPASS */
-				  CGU_PLL1_CTRL_DIRECT | /* DIRECT */
+	pll_reg &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK | CGU_PLL1_CTRL_PD_MASK | CGU_PLL1_CTRL_FBSEL_MASK |  /* CLK SEL, PowerDown , FBSEL */
+				  CGU_PLL1_CTRL_BYPASS_MASK | /* BYPASS */
+				  CGU_PLL1_CTRL_DIRECT_MASK | /* DIRECT */
 				  CGU_PLL1_CTRL_PSEL_MASK | CGU_PLL1_CTRL_MSEL_MASK | CGU_PLL1_CTRL_NSEL_MASK ); /* PSEL, MSEL, NSEL- divider ratios */
 	/* Set PLL1 up to 12MHz * 8 = 96MHz. */
 	pll_reg |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL)
 				| CGU_PLL1_CTRL_PSEL(0)
 				| CGU_PLL1_CTRL_NSEL(0)
 				| CGU_PLL1_CTRL_MSEL(7)
-				| CGU_PLL1_CTRL_FBSEL;
+				| CGU_PLL1_CTRL_FBSEL(1);
 	CGU_PLL1_CTRL = pll_reg;
 	/* wait until stable */
-	while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK));
+	while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK_MASK));
 
 	/* Wait before to switch to max speed */
 	delay(WAIT_CPU_CLOCK_INIT_DELAY);
@@ -453,20 +453,20 @@ void cpu_clock_pll1_max_speed(void)
 	/* Direct mode: FCLKOUT = FCCO = M*(FCLKIN/N) */
 	pll_reg = CGU_PLL1_CTRL;
 	/* Clear PLL1 bits */
-	pll_reg &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK | CGU_PLL1_CTRL_PD | CGU_PLL1_CTRL_FBSEL |  /* CLK SEL, PowerDown , FBSEL */
-				  CGU_PLL1_CTRL_BYPASS | /* BYPASS */
-				  CGU_PLL1_CTRL_DIRECT | /* DIRECT */
+	pll_reg &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK | CGU_PLL1_CTRL_PD_MASK | CGU_PLL1_CTRL_FBSEL_MASK |  /* CLK SEL, PowerDown , FBSEL */
+				  CGU_PLL1_CTRL_BYPASS_MASK | /* BYPASS */
+				  CGU_PLL1_CTRL_DIRECT_MASK | /* DIRECT */
 				  CGU_PLL1_CTRL_PSEL_MASK | CGU_PLL1_CTRL_MSEL_MASK | CGU_PLL1_CTRL_NSEL_MASK ); /* PSEL, MSEL, NSEL- divider ratios */
 	/* Set PLL1 up to 12MHz * 17 = 204MHz. */
 	pll_reg |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL)
 			| CGU_PLL1_CTRL_PSEL(0)
 			| CGU_PLL1_CTRL_NSEL(0)
 			| CGU_PLL1_CTRL_MSEL(16)
-			| CGU_PLL1_CTRL_FBSEL
-			| CGU_PLL1_CTRL_DIRECT;
+			| CGU_PLL1_CTRL_FBSEL(1)
+			| CGU_PLL1_CTRL_DIRECT(1);
 	CGU_PLL1_CTRL = pll_reg;
 	/* wait until stable */
-	while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK));
+	while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK_MASK));
 
 }