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Merge branch 'master' of https://github.com/mossmann/hackrf

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This commit is contained in:
Jared Boone
2012-09-04 09:24:18 -07:00
parent 8758bb05ba 129b410f4b
commit 94cffa41e5
18 changed files with 9147 additions and 5002 deletions
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2
firmware/common/max2837_regs.def
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@ -16,7 +16,7 @@
/* n=name, r=regnum, o=offset (bits from LSB), l=length (bits) */ /* n=name, r=regnum, o=offset (bits from LSB), l=length (bits) */
#define __MREG__(n,r,o,l) \ #define __MREG__(n,r,o,l) \
static inline uint16_t get_##n(void) { \ static inline uint16_t get_##n(void) { \
return (max2837_regs[r] >> o) & ((1<<l)-1); \ return (max2837_regs[r] >> (o-l+1)) & ((1<<l)-1); \
} \ } \
static inline void set_##n(uint16_t v) { \ static inline void set_##n(uint16_t v) { \
max2837_regs[r] &= ~(((1<<l)-1)<<(o-l+1)); \ max2837_regs[r] &= ~(((1<<l)-1)<<(o-l+1)); \

463
firmware/common/rffc5071.c
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@ -19,16 +19,86 @@
* Boston, MA 02110-1301, USA. * Boston, MA 02110-1301, USA.
*/ */
/*
* 'gcc -DTEST -DDEBUG -O2 -o test rffc5071.c' prints out what test
* program would do if it had a real spi library
*/
#include <stdint.h> #include <stdint.h>
#include <string.h>
#include "rffc5071.h"
#include "rffc5071_regs.def" // private register def macros
#if (defined DEBUG)
#include <stdio.h>
#define LOG printf
#else
#define LOG(x,...)
#include <libopencm3/lpc43xx/ssp.h> #include <libopencm3/lpc43xx/ssp.h>
#include <libopencm3/lpc43xx/scu.h> #include <libopencm3/lpc43xx/scu.h>
#include <libopencm3/lpc43xx/gpio.h> #include <libopencm3/lpc43xx/gpio.h>
#include "hackrf_core.h" #include "hackrf_core.h"
#include "rffc5071.h" #endif
/* Set up pins for bit-banged serial interface. */ /* Default register values. */
static uint16_t rffc5071_regs_default[RFFC5071_NUM_REGS] = {
0xbefa, /* 00 */
0x4064, /* 01 */
0x9055, /* 02 */
0x2d02, /* 03 */
0xacbf, /* 04 */
0xacbf, /* 05 */
0x0028, /* 06 */
0x0028, /* 07 */
0xff00, /* 08 */
0x8220, /* 09 */
0x0202, /* 0A */
0x4800, /* 0B */
0x1a94, /* 0C */
0xd89d, /* 0D */
0x8900, /* 0E */
0x1e84, /* 0F */
0x89d8, /* 10 */
0x9d00, /* 11 */
0x2a20, /* 12 */
0x0000, /* 13 */
0x0000, /* 14 */
0x0000, /* 15 */
0x0000, /* 16 */
0x4900, /* 17 */
0x0281, /* 18 */
0xf00f, /* 19 */
0x0000, /* 1A */
0x0000, /* 1B */
0xc840, /* 1C */
0x1000, /* 1D */
0x0005, /* 1E */ };
uint16_t rffc5071_regs[RFFC5071_NUM_REGS];
/* Mark all regsisters dirty so all will be written at init. */
uint32_t rffc5071_regs_dirty = 0x7fffffff;
/* Set up all registers according to defaults specified in docs. */
void rffc5071_init(void) void rffc5071_init(void)
{ {
LOG("# rffc5071_init\n");
memcpy(rffc5071_regs, rffc5071_regs_default, sizeof(rffc5071_regs));
rffc5071_regs_dirty = 0x7fffffff;
/* Write default register values to chip. */
rffc5071_regs_commit();
}
/*
* Set up pins for GPIO and SPI control, configure SSP peripheral for SPI, and
* set our own default register configuration.
*/
void rffc5071_setup(void)
{
rffc5071_init();
LOG("# rffc5071_setup\n");
#if !defined TEST
/* Configure GPIO pins. */ /* Configure GPIO pins. */
scu_pinmux(SCU_MIXER_ENX, SCU_GPIO_FAST); scu_pinmux(SCU_MIXER_ENX, SCU_GPIO_FAST);
scu_pinmux(SCU_MIXER_SCLK, SCU_GPIO_FAST); scu_pinmux(SCU_MIXER_SCLK, SCU_GPIO_FAST);
@ -40,68 +110,52 @@ void rffc5071_init(void)
/* set to known state */ /* set to known state */
gpio_set(PORT_MIXER, PIN_MIXER_ENX); /* active low */ gpio_set(PORT_MIXER, PIN_MIXER_ENX); /* active low */
gpio_clear(PORT_MIXER, (PIN_MIXER_SCLK | PIN_MIXER_SDATA)); gpio_clear(PORT_MIXER, (PIN_MIXER_SCLK | PIN_MIXER_SDATA));
#endif
//FIXME hard coded setup, fields not broken out
/* initial setup */ /* initial setup */
rffc5071_reg_write(RFFC5071_P2_FREQ1, 0x0000); /* put zeros in freq contol registers */
rffc5071_reg_write(RFFC5071_VCO_AUTO, 0xff00); set_RFFC5071_P2N(0);
rffc5071_reg_write(RFFC5071_CT_CAL1, 0xacbf); set_RFFC5071_P2LODIV(0);
rffc5071_reg_write(RFFC5071_CT_CAL2, 0xacbf); set_RFFC5071_P2PRESC(0);
rffc5071_reg_write(RFFC5071_TEST, 0x0005); set_RFFC5071_P2VCOSEL(0);
/* set to be configured via 3-wire interface, not control pins */ set_RFFC5071_P2N(0);
rffc5071_reg_write(RFFC5071_SDI_CTRL, 0x8000); set_RFFC5071_P2LODIV(0);
set_RFFC5071_P2PRESC(0);
set_RFFC5071_P2VCOSEL(0);
//rffc5071_reg_write(MIX_CONT, 0xc800); /* full duplex */ set_RFFC5071_P2N(0);
rffc5071_reg_write(RFFC5071_MIX_CONT, 0x4800); /* half duplex */ set_RFFC5071_P2LODIV(0);
} set_RFFC5071_P2PRESC(0);
set_RFFC5071_P2VCOSEL(0);
#define LO_MAX 5400 /* set ENBL and MODE to be configured via 3-wire interface,
#define REF_FREQ 50 * not control pins. */
set_RFFC5071_SIPIN(1);
/* configure frequency synthesizer in integer mode (lo in MHz) */ /* Initial settings for Lollipop switches, same for both
void rffc5071_config_synth_int(uint16_t lo) { * paths. These could use some #defines that iron out the
uint8_t n_lo; * (non)inverted signals.
uint8_t lodiv; *
uint16_t fvco; * bit0: SWTXB1 (!tx_bypass)
uint8_t fbkdiv; * bit1: SWRXB1 (rx_bypass)
uint16_t n; * bit2: SWTXA1 (tx_hp)
* bit3: unused (lock bit)
* bit4: SWRXA1 (rx_hp)
* bit5 SWD1 (!tx_ant)
*
* Unknown whether shift is needed. There are 7 register bits
* to hold 6 GPO bits. */
set_RFFC5071_P1GPO(0b010100<<1);
set_RFFC5071_P2GPO(0b010100<<1);
/* n_lo = int(log2(LO_MAX/lo)) */ /* send lock flag on GPO4 */
for (n_lo = 0; n_lo < 5; n_lo++) set_RFFC5071_LOCK(1);
if ((2 << n_lo) > (LO_MAX / lo))
break;
lodiv = 1 << n_lo; /* GPOs are active at all times */
fvco = lodiv * lo; set_RFFC5071_GATE(1);
if (fvco > 3200) { rffc5071_regs_commit();
fbkdiv = 4;
/* set charge pump for VCO > 3.2 GHz */
rffc5071_reg_write(RFFC5071_LF, 0xbefb);
} else {
fbkdiv = 2;
}
n = (fvco / fbkdiv) / REF_FREQ;
rffc5071_reg_write(RFFC5071_P1_FREQ1,
(n << 7) | (n_lo << 4) | (fbkdiv << 1));
rffc5071_reg_write(RFFC5071_P1_FREQ2, 0x0000);
rffc5071_reg_write(RFFC5071_P1_FREQ3, 0x0000);
rffc5071_reg_write(RFFC5071_P2_FREQ1,
(n << 7) | (n_lo << 4) | (fbkdiv << 1));
rffc5071_reg_write(RFFC5071_P2_FREQ2, 0x0000);
rffc5071_reg_write(RFFC5071_P2_FREQ3, 0x0000);
}
void rffc5071_enable_tx(void) {
rffc5071_reg_write(RFFC5071_SDI_CTRL, 0xc000); /* mixer 1 (TX) */
}
void rffc5071_enable_rx(void) {
rffc5071_reg_write(RFFC5071_SDI_CTRL, 0xe000); /* mixer 2 (RX) */
} }
void serial_delay(void) void serial_delay(void)
@ -112,73 +166,24 @@ void serial_delay(void)
__asm__("nop"); __asm__("nop");
} }
/* /* SPI register read.
* Send 25 bits: *
* first bit is ignored,
* second bit is zero for write operation,
* next 7 bits are register address,
* next 16 bits are register value.
*/
void rffc5071_reg_write(uint8_t reg, uint16_t val)
{
int bits = 25;
int msb = 1 << (bits -1);
uint32_t data = ((reg & 0x7f) << 16) | val;
/* make sure everything is starting in the correct state */
gpio_set(PORT_MIXER, PIN_MIXER_ENX);
gpio_clear(PORT_MIXER, (PIN_MIXER_SCLK | PIN_MIXER_SDATA));
/*
* The device requires two clocks while ENX is high before a serial
* transaction. This is not clearly documented.
*/
serial_delay();
gpio_set(PORT_MIXER, PIN_MIXER_SCLK);
serial_delay();
gpio_clear(PORT_MIXER, PIN_MIXER_SCLK);
serial_delay();
gpio_set(PORT_MIXER, PIN_MIXER_SCLK);
serial_delay();
gpio_clear(PORT_MIXER, PIN_MIXER_SCLK);
/* start transaction by bringing ENX low */
gpio_clear(PORT_MIXER, PIN_MIXER_ENX);
while (bits--) {
if (data & msb)
gpio_set(PORT_MIXER, PIN_MIXER_SDATA);
else
gpio_clear(PORT_MIXER, PIN_MIXER_SDATA);
data <<= 1;
serial_delay();
gpio_set(PORT_MIXER, PIN_MIXER_SCLK);
serial_delay();
gpio_clear(PORT_MIXER, PIN_MIXER_SCLK);
}
serial_delay();
gpio_set(PORT_MIXER, PIN_MIXER_ENX);
}
/*
* Send 9 bits: * Send 9 bits:
* first bit is ignored, * first bit is ignored,
* second bit is one for read operation, * second bit is one for read operation,
* next 7 bits are register address. * next 7 bits are register address.
* Then receive 16 bits (register value). * Then receive 16 bits (register value).
*/ */
uint16_t rffc5071_reg_read(uint8_t reg) uint16_t rffc5071_spi_read(uint8_t r) {
{
int bits = 9; int bits = 9;
int msb = 1 << (bits -1); int msb = 1 << (bits -1);
uint32_t data = 0x80 | (reg & 0x7f); uint32_t data = 0x80 | (r & 0x7f);
#if DEBUG
LOG("reg%d = 0\n", r);
return 0;
#else
/* make sure everything is starting in the correct state */ /* make sure everything is starting in the correct state */
gpio_set(PORT_MIXER, PIN_MIXER_ENX); gpio_set(PORT_MIXER, PIN_MIXER_ENX);
gpio_clear(PORT_MIXER, (PIN_MIXER_SCLK | PIN_MIXER_SDATA)); gpio_clear(PORT_MIXER, (PIN_MIXER_SCLK | PIN_MIXER_SDATA));
@ -245,4 +250,236 @@ uint16_t rffc5071_reg_read(uint8_t reg)
gpio_set(PORT_MIXER, PIN_MIXER_ENX); gpio_set(PORT_MIXER, PIN_MIXER_ENX);
return data; return data;
#endif /* DEBUG */
} }
/* SPI register write
*
* Send 25 bits:
* first bit is ignored,
* second bit is zero for write operation,
* next 7 bits are register address,
* next 16 bits are register value.
*/
void rffc5071_spi_write(uint8_t r, uint16_t v) {
#if DEBUG
LOG("0x%04x -> reg%d\n", v, r);
#else
int bits = 25;
int msb = 1 << (bits -1);
uint32_t data = ((reg & 0x7f) << 16) | val;
/* make sure everything is starting in the correct state */
gpio_set(PORT_MIXER, PIN_MIXER_ENX);
gpio_clear(PORT_MIXER, (PIN_MIXER_SCLK | PIN_MIXER_SDATA));
/*
* The device requires two clocks while ENX is high before a serial
* transaction. This is not clearly documented.
*/
serial_delay();
gpio_set(PORT_MIXER, PIN_MIXER_SCLK);
serial_delay();
gpio_clear(PORT_MIXER, PIN_MIXER_SCLK);
serial_delay();
gpio_set(PORT_MIXER, PIN_MIXER_SCLK);
serial_delay();
gpio_clear(PORT_MIXER, PIN_MIXER_SCLK);
/* start transaction by bringing ENX low */
gpio_clear(PORT_MIXER, PIN_MIXER_ENX);
while (bits--) {
if (data & msb)
gpio_set(PORT_MIXER, PIN_MIXER_SDATA);
else
gpio_clear(PORT_MIXER, PIN_MIXER_SDATA);
data <<= 1;
serial_delay();
gpio_set(PORT_MIXER, PIN_MIXER_SCLK);
serial_delay();
gpio_clear(PORT_MIXER, PIN_MIXER_SCLK);
}
serial_delay();
gpio_set(PORT_MIXER, PIN_MIXER_ENX);
#endif
}
uint16_t rffc5071_reg_read(uint8_t r)
{
/* Readback register is not cached. */
if (r == RFFC5071_READBACK_REG)
return rffc5071_spi_read(r);
/* Discard uncommited write when reading. This shouldn't
* happen, and probably has not been tested. */
if ((rffc5071_regs_dirty >> r) & 0x1) {
rffc5071_spi_read(r);
};
return rffc5071_regs[r];
}
void rffc5071_reg_write(uint8_t r, uint16_t v)
{
rffc5071_regs[r] = v;
rffc5071_spi_write(r, v);
RFFC5071_REG_SET_CLEAN(r);
}
static inline void rffc5071_reg_commit(uint8_t r)
{
rffc5071_reg_write(r,rffc5071_regs[r]);
}
void rffc5071_regs_commit(void)
{
int r;
for(r = 0; r < RFFC5071_NUM_REGS; r++) {
if ((rffc5071_regs_dirty >> r) & 0x1) {
rffc5071_reg_commit(r);
}
}
}
void rffc5071_tx(void) {
LOG("# rffc5071_tx\n");
set_RFFC5071_ENBL(0);
set_RFFC5071_FULLD(0);
set_RFFC5071_MODE(0); /* mixer 1 only (TX) */
rffc5071_regs_commit();
rffc5071_enable();
}
void rffc5071_rx(void) {
LOG("# rfc5071_rx\n");
set_RFFC5071_ENBL(0);
set_RFFC5071_FULLD(0);
set_RFFC5071_MODE(1); /* mixer 2 only (RX) */
rffc5071_regs_commit();
rffc5071_enable();
}
void rffc5071_rxtx(void) {
LOG("# rfc5071_rxtx\n");
set_RFFC5071_ENBL(0);
set_RFFC5071_FULLD(1); /* mixer 1 and mixer 2 (RXTX) */
rffc5071_regs_commit();
rffc5071_enable();
}
void rffc5071_disable(void) {
LOG("# rfc5071_disable\n");
set_RFFC5071_ENBL(0);
rffc5071_regs_commit();
}
void rffc5071_enable(void) {
LOG("# rfc5071_enable\n");
set_RFFC5071_ENBL(1);
rffc5071_regs_commit();
}
#define LO_MAX 5400
#define REF_FREQ 50
/* configure frequency synthesizer in integer mode (lo in MHz) */
uint16_t rffc5071_config_synth_int(uint16_t lo) {
uint8_t lodiv;
uint16_t fvco;
uint8_t fbkdiv;
uint16_t n;
uint16_t tune_freq;
LOG("# config_synth_int\n");
/* Calculate n_lo */
uint8_t n_lo = 0;
uint16_t x = LO_MAX / lo;
while (x > 1) {
n_lo++;
x >>= 1;
}
lodiv = 1 << n_lo;
fvco = lodiv * lo;
/* higher divider and charge pump current required above
* 3.2GHz. Programming guide says these values (fbkdiv, n,
* maybe pump?) can be changed back after enable in order to
* improve phase noise, since the VCO will already be stable
* and will be unaffected. */
if (fvco > 3200) {
fbkdiv = 4;
set_RFFC5071_PLLCPL(3);
} else {
fbkdiv = 2;
set_RFFC5071_PLLCPL(2);
}
n = (fvco / fbkdiv) / REF_FREQ;
tune_freq = 50*n*fbkdiv/lodiv;
LOG("# lo=%d n_lo=%d lodiv=%d fvco=%d fbkdiv=%d n=%d tune_freq=%d\n",
lo, n_lo, lodiv, fvco, fbkdiv, n, tune_freq);
/* Path 1 */
set_RFFC5071_P1LODIV(lodiv);
set_RFFC5071_P1N(n);
set_RFFC5071_P1PRESC(fbkdiv >> 1);
set_RFFC5071_P1NMSB(0);
set_RFFC5071_P1NLSB(0);
/* Path 2 */
set_RFFC5071_P2LODIV(lodiv);
set_RFFC5071_P2N(n);
set_RFFC5071_P2PRESC(fbkdiv >> 1);
set_RFFC5071_P2NMSB(0);
set_RFFC5071_P2NLSB(0);
rffc5071_regs_commit();
return tune_freq;
}
/* !!!!!!!!!!! hz is currently ignored !!!!!!!!!!!
*
* Tuning is rounded down to the nearest 25MHz or 50MHz depending on
* frequency requsted. Actual tuned value in MHz is returned. */
uint16_t rffc5071_set_frequency(uint16_t mhz, uint32_t hz) {
uint16_t tune_freq;
rffc5071_disable();
tune_freq = rffc5071_config_synth_int(mhz);
rffc5071_enable();
return tune_freq;
}
#ifdef TEST
int main(int ac, char **av)
{
rffc5071_setup();
rffc5071_tx();
rffc5071_set_frequency(500, 0);
rffc5071_set_frequency(525, 0);
rffc5071_set_frequency(550, 0);
rffc5071_set_frequency(1500, 0);
rffc5071_set_frequency(1525, 0);
rffc5071_set_frequency(1550, 0);
rffc5071_disable();
rffc5071_rx();
rffc5071_disable();
rffc5071_rxtx();
rffc5071_disable();
}
#endif //TEST

82
firmware/common/rffc5071.h
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@ -19,45 +19,47 @@
* Boston, MA 02110-1301, USA. * Boston, MA 02110-1301, USA.
*/ */
#include <stdint.h> #ifndef __RFFC5071_H
#define __RFFC5071_H
/* register names */ /* 31 registers, each containing 16 bits of data. */
#define RFFC5071_LF 0x00 #define RFFC5071_NUM_REGS 31
#define RFFC5071_XO 0x01
#define RFFC5071_CAL_TIME 0x02
#define RFFC5071_VCO_CTRL 0x03
#define RFFC5071_CT_CAL1 0x04
#define RFFC5071_CT_CAL2 0x05
#define RFFC5071_PLL_CAL1 0x06
#define RFFC5071_PLL_CAL2 0x07
#define RFFC5071_VCO_AUTO 0x08
#define RFFC5071_PLL_CTRL 0x09
#define RFFC5071_PLL_BIAS 0x0A
#define RFFC5071_MIX_CONT 0x0B
#define RFFC5071_P1_FREQ1 0x0C
#define RFFC5071_P1_FREQ2 0x0D
#define RFFC5071_P1_FREQ3 0x0E
#define RFFC5071_P2_FREQ1 0x0F
#define RFFC5071_P2_FREQ2 0x10
#define RFFC5071_P2_FREQ3 0x11
#define RFFC5071_FN_CTRL 0x12
#define RFFC5071_EXT_MOD 0x13
#define RFFC5071_FMOD 0x14
#define RFFC5071_SDI_CTRL 0x15
#define RFFC5071_GPO 0x16
#define RFFC5071_T_VCO 0x17
#define RFFC5071_IQMOD1 0x18
#define RFFC5071_IQMOD2 0x19
#define RFFC5071_IQMOD3 0x1A
#define RFFC5071_IQMOD4 0x1B
#define RFFC5071_T_CTRL 0x1C
#define RFFC5071_DEV_CTRL 0x1D
#define RFFC5071_TEST 0x1E
#define RFFC5071_READBACK 0x1F
void rffc5071_init(void); extern uint16_t rffc5071_regs[RFFC5071_NUM_REGS];
void rffc5071_config_synth_int(uint16_t lo); extern uint32_t rffc5071_regs_dirty;
void rffc5071_enable_tx(void);
void rffc5071_enable_rx(void); #define RFFC5071_REG_SET_CLEAN(r) rffc5071_regs_dirty &= ~(1UL<<r)
void rffc5071_reg_write(uint8_t reg, uint16_t val); #define RFFC5071_REG_SET_DIRTY(r) rffc5071_regs_dirty |= (1UL<<r)
uint16_t rffc5071_reg_read(uint8_t reg);
/* Initialize chip. Call _setup() externally, as it calls _init(). */
extern void rffc5071_init(void);
extern void rffc5071_setup(void);
/* Read a register via SPI. Save a copy to memory and return
* value. Discard any uncommited changes and mark CLEAN. */
extern uint16_t rffc5071_reg_read(uint8_t r);
/* Write value to register via SPI and save a copy to memory. Mark
* CLEAN. */
extern void rffc5071_reg_write(uint8_t r, uint16_t v);
/* Write all dirty registers via SPI from memory. Mark all clean. Some
* operations require registers to be written in a certain order. Use
* provided routines for those operations. */
extern void rffc5071_regs_commit(void);
/* Set frequency (MHz). The 'hz' field is currently ignored. Actual
* tune frequency (MHz) is returned. Expect requested freq to be
* rounded down to the nearest multiple of 25MHz or 50MHz, depending
* internal calculations. */
extern uint16_t rffc5071_set_frequency(uint16_t mhz, uint32_t hz);
/* Set up rx only, tx only, or full duplex. Chip should be disabled
* before _tx, _rx, or _rxtx are called. */
extern void rffc5071_tx(void);
extern void rffc5071_rx(void);
extern void rffc5071_rxtx(void);
extern void rffc5071_enable(void);
extern void rffc5071_disable(void);
#endif // __RFFC5071_H

257
firmware/common/rffc5071_regs.def Normal file
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@ -0,0 +1,257 @@
/* -*- mode: c -*-
*
* Copyright 2012 Michael Ossmann
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#ifndef __RFFC5071_REGS_DEF
#define __RFFC5071_REGS_DEF
#define RFFC5071_READBACK_REG 31
/* Generate static inline accessors that operate on the global
* regs. Done this way to (1) allow defs to be scraped out and used
* elsewhere, e.g. in scripts, (2) to avoid dealing with endian
* (structs). This may be used in firmware, or on host predefined
* register loads. */
/* On set_, register is always set dirty, even if nothing
* changed. This makes sure that writes that have side effects,
* e.g. frequency setting, are not skipped. */
/* n=name, r=regnum, o=offset (bits from LSB) of LSB of field,
* l=length (bits) */
#define __MREG__(n,r,o,l) \
static inline uint16_t get_##n(void) { \
return (rffc5071_regs[r] >> o) & ((1<<l)-1); \
} \
static inline void set_##n(uint16_t v) { \
rffc5071_regs[r] &= ~(((1<<l)-1)<<o); \
rffc5071_regs[r] |= ((v&((1<<l)-1))<<o); \
RFFC5071_REG_SET_DIRTY(r); \
}
/* REG 00 (0): LF */
__MREG__(RFFC5071_PLLCPL,0,0,3)
__MREG__(RFFC5071_P1CPDEF,0,3,6)
__MREG__(RFFC5071_P2CPDEF,0,9,6)
__MREG__(RFFC5071_IFACT,0,15,1)
#define RFFC5071_
/* REG 01 (1): XO */
__MREG__(RFFC5071_SUWAIT,1,0,10)
__MREG__(RFFC5071_XOCF,1,10,1)
__MREG__(RFFC5071_XOC,1,11,4)
__MREG__(RFFC5071_XOCH,1,15,1)
/* REG 02 (2): CAL_TIME */
__MREG__(RFFC5071_TKV2,2,0,4)
__MREG__(RFFC5071_TKV1,2,4,4)
__MREG__(RFFC5071_TCT,2,10,5)
__MREG__(RFFC5071_WAIT,2,15,1)
/* REG 03 (3): VCO_CTRL */
__MREG__(RFFC5071_ICPUP,3,1,2)
__MREG__(RFFC5071_REFST,3,3,1)
__MREG__(RFFC5071_XOI3,3,4,1)
__MREG__(RFFC5071_XOI2,3,5,1)
__MREG__(RFFC5071_XOI1,3,6,1)
__MREG__(RFFC5071_KVPOL,3,7,1)
__MREG__(RFFC5071_KVRNG,3,8,1)
__MREG__(RFFC5071_KVAVG,3,9,2)
__MREG__(RFFC5071_CLKPL,3,1,1)
__MREG__(RFFC5071_CTPOL,3,12,1)
__MREG__(RFFC5071_CTAVG,3,13,2)
__MREG__(RFFC5071_XTVCO,3,15,1)
/* REG 04 (4): CT_CAL1 */
__MREG__(RFFC5071_P1CTDEF,4,0,7)
__MREG__(RFFC5071_P1CT,4,7,1)
__MREG__(RFFC5071_P1CTV,4,8,5)
__MREG__(RFFC5071_P1CTGAIN,4,13,3)
/* REG 05 (5): CT_CAL2 */
__MREG__(RFFC5071_P2CTDEF,5,0,7)
__MREG__(RFFC5071_P2CT,5,7,1)
__MREG__(RFFC5071_P2CTV,5,8,5)
__MREG__(RFFC5071_P2CTGAIN,5,13,3)
/* REG 06 (6): PLL_CAL1 */
__MREG__(RFFC5071_P1SGN,6,2,1)
__MREG__(RFFC5071_P1KVGAIN,6,3,3)
__MREG__(RFFC5071_P1DN,6,6,9)
__MREG__(RFFC5071_P1KV,6,15,1)
/* REG 07 (7): PLL_CAL2 */
__MREG__(RFFC5071_P2SGN,7,2,1)
__MREG__(RFFC5071_P2KVGAIN,7,3,3)
__MREG__(RFFC5071_P2DB,7,6,9)
__MREG__(RFFC5071_P2KV,7,15,1)
/* REG 08 (8): VCO_AUTO */
__MREG__(RFFC5071_CTMIN,8,1,7)
__MREG__(RFFC5071_CTMAX,8,8,7)
__MREG__(RFFC5071_AUTO,8,15,1)
/* REG 09 (9): PLL_CTRL */
__MREG__(RFFC5071_PLLDY,9,0,2)
__MREG__(RFFC5071_ALOI,9,2,1)
__MREG__(RFFC5071_RELOK,9,3,1)
__MREG__(RFFC5071_LDLEV,9,4,1)
__MREG__(RFFC5071_LDEN,9,5,1)
__MREG__(RFFC5071_TVCO,9,6,5)
__MREG__(RFFC5071_PLLST,9,11,1)
__MREG__(RFFC5071_CLKDIV,9,12,3)
__MREG__(RFFC5071_DIVBY,9,15,1)
/* REG 0A (10): PLL_BIAS */
__MREG__(RFFC5071_P2VCOI,10,0,3)
__MREG__(RFFC5071_P2LOI,10,3,4)
__MREG__(RFFC5071_P1VCOI,10,8,3)
__MREG__(RFFC5071_P1LOI,10,11,4)
/* REG 0B (11): MIX_CONT */
__MREG__(RFFC5071_P2MIXIDD,11,9,3)
__MREG__(RFFC5071_P1MIXIDD,11,12,3)
__MREG__(RFFC5071_FULLD,11,15,1)
/* REG 0C (12): P1_FREQ1 */
__MREG__(RFFC5071_P1VCOSEL,12,0,2)
__MREG__(RFFC5071_P1PRESC,12,2,2)
__MREG__(RFFC5071_P1LODIV,12,4,3)
__MREG__(RFFC5071_P1N,12,7,9)
/* REG 0D (13): P1_FREQ2 */ /* !!!!! CHECK FOR OVERFLOW !!!!! */
__MREG__(RFFC5071_P1NMSB,13,0,16)
/* REG 0E (14): P1_FREQ3 */
__MREG__(RFFC5071_P1NLSB,14,8,8)
/* REG 0F (15): P2_FREQ1 */
__MREG__(RFFC5071_P2VCOSEL,15,0,2)
__MREG__(RFFC5071_P2PRESC,15,2,2)
__MREG__(RFFC5071_P2LODIV,15,4,3)
__MREG__(RFFC5071_P2N,15,7,9)
/* REG 10 (16): P2_FREQ2 */ /* !!!!! CHECK FOR OVERFLOW !!!!! */
__MREG__(RFFC5071_P2NMSB,16,0,16)
/* REG 11 (17): P2_FREQ3 */
__MREG__(RFFC5071_P2NLSB,17,8,8)
/* REG 12 (18): FN_CTRL */
__MREG__(RFFC5071_TZPS,18,1,1)
__MREG__(RFFC5071_DMODE,18,2,1)
__MREG__(RFFC5071_FM,18,3,1)
__MREG__(RFFC5071_DITH,18,4,1)
__MREG__(RFFC5071_DSM_MODE,18,5,1)
__MREG__(RFFC5071_PHSALNDLY,18,6,2)
__MREG__(RFFC5071_PHSALNGAIN,18,8,3)
__MREG__(RFFC5071_PHALN,18,11,1)
__MREG__(RFFC5071_SDM,18,12,2)
__MREG__(RFFC5071_DITHR,18,14,1)
__MREG__(RFFC5071_FNZ,18,15,1)
/* REG 13 (19): EXT_MOD */
__MREG__(RFFC5071_MODSTEP,19,10,4)
__MREG__(RFFC5071_MODSETUP,19,14,2)
/* REG 14 (20): FMOD */ /* !!!!! CHECK FOR OVERFLOW !!!!! */
__MREG__(RFFC5071_MODULATION,20,0,16)
/* REG 15 (21): SDI_CTRL */
__MREG__(RFFC5071_RESET,21,1,1)
__MREG__(RFFC5071_ADDR,21,11,1)
__MREG__(RFFC5071_4WIRE,21,12,1)
__MREG__(RFFC5071_MODE,21,13,1)
__MREG__(RFFC5071_ENBL,21,14,1)
__MREG__(RFFC5071_SIPIN,21,15,1)
/* REG 16 (22): GPO */
__MREG__(RFFC5071_LOCK,22,0,1)
__MREG__(RFFC5071_GATE,22,1,1)
__MREG__(RFFC5071_P1GPO,22,2,7)
__MREG__(RFFC5071_P2GPO,22,9,7)
/* REG 17 (23): T_VCO */
__MREG__(RFFC5071_CURVE_VCO3,23,7,3)
__MREG__(RFFC5071_CURVE_VCO2,23,10,3)
__MREG__(RFFC5071_CURVE_VCO1,23,13,3)
/* REG 18 (24): IQMOD1 */
__MREG__(RFFC5071_BUFDC,24,0,2)
__MREG__(RFFC5071_DIVBIAS,24,2,1)
__MREG__(RFFC5071_CALBLK,24,3,1)
__MREG__(RFFC5071_CALNUL,24,4,1)
__MREG__(RFFC5071_CALON,24,5,1)
__MREG__(RFFC5071_LOBIAS,24,6,2)
__MREG__(RFFC5071_MODBIAS,24,8,3)
__MREG__(RFFC5071_CTRL,24,11,5) /* shown as 5 fields in reg overview */
/* REG 19 (25): IQMOD2 */
__MREG__(RFFC5071_MODBUF,25,0,2)
__MREG__(RFFC5071_MOD,25,2,2)
__MREG__(RFFC5071_CALATTEN,25,4,2)
__MREG__(RFFC5071_RCTUNE,25,6,6)
__MREG__(RFFC5071_BBATTEN,25,12,4)
/* REG 1A (26): IQMOD3 */
__MREG__(RFFC5071_DACEN,26,3,1)
__MREG__(RFFC5071_BUFDACQ,26,4,6)
__MREG__(RFFC5071_BUFDACI,26,10,6)
/* REG 1B (27): IQMOD4 */
__MREG__(RFFC5071_BUFBIAS2,27,2,2)
__MREG__(RFFC5071_BUFBIAS1,27,4,2)
__MREG__(RFFC5071_MODDACQ,27,6,6)
__MREG__(RFFC5071_MODDACI,27,12,6)
/* REG 1C (28): T_CTRL */
__MREG__(RFFC5071_V_TEST,28,5,1)
__MREG__(RFFC5071_LDO_BY,28,6,1)
__MREG__(RFFC5071_EXT_FILT,28,7,1)
__MREG__(RFFC5071_REF_SEL,28,8,1)
__MREG__(RFFC5071_FILT_CTRL,28,9,2)
__MREG__(RFFC5071_FC_EN,28,11,1)
__MREG__(RFFC5071_TBL_SEL,28,12,2)
__MREG__(RFFC5071_TC_EN,28,14,2)
/* REG 1D (29): DEV_CTRL */
__MREG__(RFFC5071_BYPAS,29,1,1)
__MREG__(RFFC5071_CTCLK,29,2,1)
__MREG__(RFFC5071_DAC,29,3,1)
__MREG__(RFFC5071_CPD,29,4,1)
__MREG__(RFFC5071_CPU,29,5,1)
__MREG__(RFFC5071_RSMSTOPST,29,6,5)
__MREG__(RFFC5071_RSMST,29,11,1)
__MREG__(RFFC5071_READSEL,29,12,4)
/* REG 1E (30): TEST */
__MREG__(RFFC5071_LFSRD,30,0,1) /* n/a in reg overview */
__MREG__(RFFC5071_RCBYP,30,1,1)
__MREG__(RFFC5071_RGBYP,30,2,1)
__MREG__(RFFC5071_LFSRT,30,3,1)
__MREG__(RFFC5071_LFSRGATET,30,4,4)
__MREG__(RFFC5071_LFSRP,30,8,1)
__MREG__(RFFC5071_LFSR,30,9,1)
__MREG__(RFFC5071_TSEL,30,10,2)
__MREG__(RFFC5071_TMUX,30,12,3)
__MREG__(RFFC5071_TEN,30,15,1)
#endif // __RFFC5071_REGS_DEF

5
firmware/mixertx/mixertx.c
View File

@ -35,14 +35,13 @@ int main(void)
pin_setup(); pin_setup();
gpio_set(PORT_EN1V8, PIN_EN1V8); /* 1V8 on */ gpio_set(PORT_EN1V8, PIN_EN1V8); /* 1V8 on */
cpu_clock_init(); cpu_clock_init();
ssp1_init(); ssp1_init();
gpio_set(PORT_LED1_3, (PIN_LED1)); /* LED1 on */ gpio_set(PORT_LED1_3, (PIN_LED1)); /* LED1 on */
ssp1_set_mode_max2837(); ssp1_set_mode_max2837();
max2837_setup(); max2837_setup();
rffc5071_init(); rffc5071_setup();
rffc5071_reg_write(RFFC5071_GPO, 0x0001); /* PLL lock output on GPO4 */
gpio_set(PORT_LED1_3, (PIN_LED2)); /* LED2 on */ gpio_set(PORT_LED1_3, (PIN_LED2)); /* LED2 on */
max2837_set_frequency(freq); max2837_set_frequency(freq);

10
firmware/sgpio-rx/sgpio-rx.c
View File

@ -279,10 +279,11 @@ int main(void) {
ssp1_init(); ssp1_init();
ssp1_set_mode_max2837(); ssp1_set_mode_max2837();
max2837_setup(); max2837_setup();
rffc5071_init(); rffc5071_setup();
rffc5071_config_synth_int(500); rffc5071_rx();
rffc5071_enable_rx(); rffc5071_set_frequency(500, 0); // 500 MHz, 0 Hz (Hz ignored)
//rffc5071_reg_write(RFFC5071_GPO, 0x0001); /* PLL lock output on GPO4 */
#ifdef LOLLIPOP_SWITCH_SET_UP_DONE_IN_RFFC5071
/* lollipop */ /* lollipop */
uint8_t gpo = uint8_t gpo =
(1 << 0) /* SWTXB1 (!tx_bypass) */ (1 << 0) /* SWTXB1 (!tx_bypass) */
@ -301,6 +302,7 @@ int main(void) {
//| (0 << 5); /* !AMP_PWR */ //| (0 << 5); /* !AMP_PWR */
rffc5071_reg_write(RFFC5071_GPO, (gpo << 9) | (gpo << 2) | 0x3); rffc5071_reg_write(RFFC5071_GPO, (gpo << 9) | (gpo << 2) | 0x3);
gpio_set(PORT_LED1_3, (PIN_LED1)); /* LED1 on */ gpio_set(PORT_LED1_3, (PIN_LED1)); /* LED1 on */
#endif
max2837_set_frequency(freq); max2837_set_frequency(freq);
max2837_start(); max2837_start();

2865
hardware/jawbreaker/baseband.sch
View File

File diff suppressed because it is too large Load Diff

3299
hardware/jawbreaker/frontend.sch Normal file
View File

File diff suppressed because it is too large Load Diff

365
hardware/jawbreaker/jawbreaker-cache.lib
View File

@ -1,4 +1,4 @@
EESchema-LIBRARY Version 2.3 Date: Sat Aug 25 00:58:51 2012 EESchema-LIBRARY Version 2.3 Date: Tue Sep 4 10:12:04 2012
#encoding utf-8 #encoding utf-8
# #
# +1.8V # +1.8V
@ -46,6 +46,28 @@ X PM 5 -400 0 300 R 60 60 1 1 P
ENDDRAW ENDDRAW
ENDDEF ENDDEF
# #
# BALUN-B0310J50100AHF
#
DEF BALUN-B0310J50100AHF T 0 40 Y N 1 F N
F0 "T" 0 200 70 H V C CNN
F1 "BALUN-B0310J50100AHF" 0 -150 70 H V C CNN
DRAW
A -150 -50 50 1 1799 0 1 0 N -100 -50 -200 -50
A -150 100 50 -1799 -1 0 1 0 N -200 100 -100 100
A -50 -50 50 1 1799 0 1 0 N 0 -50 -100 -50
A -50 100 50 -1799 -1 0 1 0 N -100 100 0 100
A 50 -50 50 1 1799 0 1 0 N 100 -50 0 -50
A 50 100 50 -1799 -1 0 1 0 N 0 100 100 100
A 150 -50 50 1 1799 0 1 0 N 200 -50 100 -50
A 150 100 50 -1799 -1 0 1 0 N 100 100 200 100
A 150 100 50 -1799 -1 0 1 0 N 100 100 200 100
X S1 1 300 100 100 L 60 60 1 1 P
X S2 2 300 -50 100 L 60 60 1 1 P
X PR1 3 -300 100 100 R 60 60 1 1 P
X PR2 4 -300 -50 100 R 60 60 1 1 P
ENDDRAW
ENDDEF
#
# C # C
# #
DEF C C 0 10 N Y 1 F N DEF C C 0 10 N Y 1 F N
@ -76,83 +98,6 @@ X 1 1 -150 0 100 R 60 60 1 1 P
ENDDRAW ENDDRAW
ENDDEF ENDDEF
# #
# CONN_12X2
#
DEF CONN_12X2 P 0 10 Y N 1 F N
F0 "P" 0 650 60 H V C CNN
F1 "CONN_12X2" 0 0 50 V V C CNN
DRAW
S -100 600 100 -600 0 1 0 N
X P1 1 -400 550 300 R 60 30 1 1 P I
X P2 2 400 550 300 L 60 30 1 1 P I
X P3 3 -400 450 300 R 60 30 1 1 P I
X P4 4 400 450 300 L 60 30 1 1 P I
X P5 5 -400 350 300 R 60 30 1 1 P I
X P6 6 400 350 300 L 60 30 1 1 P I
X P7 7 -400 250 300 R 60 30 1 1 P I
X P8 8 400 250 300 L 60 30 1 1 P I
X P9 9 -400 150 300 R 60 30 1 1 P I
X P10 10 400 150 300 L 60 30 1 1 P I
X P20 20 400 -350 300 L 60 30 1 1 P I
X P11 11 -400 50 300 R 60 30 1 1 P I
X P21 21 -400 -450 300 R 60 30 1 1 P I
X P12 12 400 50 300 L 60 30 1 1 P I
X P22 22 400 -450 300 L 60 30 1 1 P I
X P13 13 -400 -50 300 R 60 30 1 1 P I
X P23 23 -400 -550 300 R 60 30 1 1 P I
X P14 14 400 -50 300 L 60 30 1 1 P I
X P24 24 400 -550 300 L 60 30 1 1 P I
X P15 15 -400 -150 300 R 60 30 1 1 P I
X P16 16 400 -150 300 L 60 30 1 1 P I
X P17 17 -400 -250 300 R 60 30 1 1 P I
X P18 18 400 -250 300 L 60 30 1 1 P I
X P19 19 -400 -350 300 R 60 30 1 1 P I
ENDDRAW
ENDDEF
#
# CONN_16X2
#
DEF CONN_16X2 P 0 10 Y N 1 F N
F0 "P" 0 850 60 H V C CNN
F1 "CONN_16X2" 0 0 50 V V C CNN
DRAW
S -100 800 100 -800 0 1 0 N
S 1200 650 1200 650 0 1 0 N
X P1 1 -400 750 300 R 60 30 1 1 P I
X P2 2 400 750 300 L 60 30 1 1 P I
X P3 3 -400 650 300 R 60 30 1 1 P I
X P4 4 400 650 300 L 60 30 1 1 P I
X P5 5 -400 550 300 R 60 30 1 1 P I
X P6 6 400 550 300 L 60 30 1 1 P I
X P7 7 -400 450 300 R 60 30 1 1 P I
X P8 8 400 450 300 L 60 30 1 1 P I
X P9 9 -400 350 300 R 60 30 1 1 P I
X P10 10 400 350 300 L 60 30 1 1 P I
X P20 20 400 -150 300 L 60 30 1 1 P I
X P30 30 400 -650 300 L 60 30 1 1 P I
X P11 11 -400 250 300 R 60 30 1 1 P I
X P21 21 -400 -250 300 R 60 30 1 1 P I
X P31 31 -400 -750 300 R 60 30 1 1 P I
X P12 12 400 250 300 L 60 30 1 1 P I
X P22 22 400 -250 300 L 60 30 1 1 P I
X P32 32 400 -750 300 L 60 30 1 1 P I
X P13 13 -400 150 300 R 60 30 1 1 P I
X P23 23 -400 -350 300 R 60 30 1 1 P I
X P14 14 400 150 300 L 60 30 1 1 P I
X P24 24 400 -350 300 L 60 30 1 1 P I
X P15 15 -400 50 300 R 60 30 1 1 P I
X ~ 25 -400 -450 300 R 60 30 1 1 P I
X P16 16 400 50 300 L 60 30 1 1 P I
X P26 26 400 -450 300 L 60 30 1 1 P I
X P17 17 -400 -50 300 R 60 30 1 1 P I
X P27 27 -400 -550 300 R 60 30 1 1 P I
X P18 18 400 -50 300 L 60 30 1 1 P I
X P28 28 400 -550 300 L 60 30 1 1 P I
X P19 19 -400 -150 300 R 60 30 1 1 P I
X P29 29 -400 -650 300 R 60 30 1 1 P I
ENDDRAW
ENDDEF
#
# CONN_2 # CONN_2
# #
DEF CONN_2 P 0 40 Y N 1 F N DEF CONN_2 P 0 40 Y N 1 F N
@ -165,6 +110,19 @@ X PM 2 -350 -100 250 R 60 60 1 1 P I
ENDDRAW ENDDRAW
ENDDEF ENDDEF
# #
# CONN_3
#
DEF CONN_3 K 0 40 Y N 1 F N
F0 "K" -50 0 50 V V C CNN
F1 "CONN_3" 50 0 40 V V C CNN
DRAW
S -100 150 100 -150 0 1 0 N
X P1 1 -350 100 250 R 60 60 1 1 P I
X PM 2 -350 0 250 R 60 60 1 1 P I
X P3 3 -350 -100 250 R 60 60 1 1 P I
ENDDRAW
ENDDEF
#
# CONN_3X2 # CONN_3X2
# #
DEF CONN_3X2 P 0 40 Y N 1 F N DEF CONN_3X2 P 0 40 Y N 1 F N
@ -283,6 +241,34 @@ X ~ 16 400 -350 300 L 60 60 1 1 P I
ENDDRAW ENDDRAW
ENDDEF ENDDEF
# #
# FIL-DEA
#
DEF FIL-DEA U 0 40 Y Y 1 F N
F0 "U" 0 50 60 H V C CNN
F1 "FIL-DEA" 0 -50 60 H V C CNN
DRAW
S -300 200 300 -200 0 1 0 N
X IN 1 -600 -150 300 R 50 50 1 1 B
X GND 2 600 -150 300 L 50 50 1 1 W
X OUT 3 600 150 300 L 50 50 1 1 B
X GND 4 -600 150 300 R 50 50 1 1 W
ENDDRAW
ENDDEF
#
# FIL-LP0603
#
DEF FIL-LP0603 U 0 40 Y Y 1 F N
F0 "U" 0 50 60 H V C CNN
F1 "FIL-LP0603" 0 -50 60 H V C CNN
DRAW
S -300 200 300 -200 0 1 0 N
X OUT 1 -600 150 300 R 50 50 1 1 B
X GND 2 -600 -150 300 R 50 50 1 1 W
X GND 3 600 -150 300 L 50 50 1 1 W
X IN 4 600 150 300 L 50 50 1 1 B
ENDDRAW
ENDDEF
#
# FILTER # FILTER
# #
DEF FILTER FB 0 40 Y N 1 F N DEF FILTER FB 0 40 Y N 1 F N
@ -311,6 +297,88 @@ X GND 1 0 0 0 U 30 30 1 1 W N
ENDDRAW ENDDRAW
ENDDEF ENDDEF
# #
# GSG-74HC04
#
DEF GSG-74HC04 U 0 40 Y Y 1 F N
F0 "U" -50 0 60 V V C CNN
F1 "GSG-74HC04" 50 0 60 V V C CNN
DRAW
S -300 350 300 -350 0 1 0 N
X ~ 0 0 -650 300 U 50 50 1 1 W
X 1A 1 -600 300 300 R 50 50 1 1 I
X 1Y 2 -600 200 300 R 50 50 1 1 O
X 2A 3 -600 100 300 R 50 50 1 1 I
X 2Y 4 -600 0 300 R 50 50 1 1 O
X 3A 5 -600 -100 300 R 50 50 1 1 I
X 3Y 6 -600 -200 300 R 50 50 1 1 O
X GND 7 -600 -300 300 R 50 50 1 1 W
X 4Y 8 600 -300 300 L 50 50 1 1 O
X 4A 9 600 -200 300 L 50 50 1 1 I
X 5Y 10 600 -100 300 L 50 50 1 1 O
X 5A 11 600 0 300 L 50 50 1 1 I
X 6Y 12 600 100 300 L 50 50 1 1 O
X 6A 13 600 200 300 L 50 50 1 1 I
X VCC 14 600 300 300 L 50 50 1 1 W
ENDDRAW
ENDDEF
#
# GSG-74HC08
#
DEF GSG-74HC08 U 0 40 Y Y 1 F N
F0 "U" -50 0 60 V V C CNN
F1 "GSG-74HC08" 50 0 60 V V C CNN
DRAW
S -300 350 300 -350 0 1 0 N
X ~ 0 0 -650 300 U 50 50 1 1 W
X 1A 1 -600 300 300 R 50 50 1 1 I
X 1B 2 -600 200 300 R 50 50 1 1 I
X 1Y 3 -600 100 300 R 50 50 1 1 O
X 2A 4 -600 0 300 R 50 50 1 1 I
X 2B 5 -600 -100 300 R 50 50 1 1 I
X 2Y 6 -600 -200 300 R 50 50 1 1 O
X GND 7 -600 -300 300 R 50 50 1 1 W
X 3Y 8 600 -300 300 L 50 50 1 1 O
X 3A 9 600 -200 300 L 50 50 1 1 I
X 3B 10 600 -100 300 L 50 50 1 1 I
X 4Y 11 600 0 300 L 50 50 1 1 O
X 4A 12 600 100 300 L 50 50 1 1 I
X 4B 13 600 200 300 L 50 50 1 1 I
X VCC 14 600 300 300 L 50 50 1 1 W
ENDDRAW
ENDDEF
#
# GSG-900MHZ-F-ANTENNA
#
DEF GSG-900MHZ-F-ANTENNA J 0 40 Y Y 1 F N
F0 "J" 300 100 60 H V C CNN
F1 "GSG-900MHZ-F-ANTENNA" 250 650 60 H V C CNN
DRAW
P 4 0 1 0 -150 300 -150 550 0 550 0 300 N
P 15 0 1 0 0 550 100 550 100 200 200 200 200 550 300 550 300 200 400 200 400 550 500 550 500 200 600 200 600 550 700 550 700 100 N
X RF 1 0 0 300 U 50 50 1 1 B
X GND 2 -150 0 300 U 50 50 1 1 W
ENDDRAW
ENDDEF
#
# GSG-DIODE-TVS-BI
#
DEF GSG-DIODE-TVS-BI D 0 40 N N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "GSG-DIODE-TVS-BI" 0 -100 40 H V C CNN
$FPLIST
D?
SO*
SM*
$ENDFPLIST
DRAW
P 5 0 1 8 -20 50 0 30 0 -30 20 -50 20 -50 N
P 5 0 1 0 0 0 -100 50 -100 -50 0 0 0 0 F
P 5 0 1 0 0 0 100 50 100 -50 0 0 0 0 F
X A 1 -250 0 150 R 40 40 1 1 P
X K 2 250 0 150 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# GSG-IP4220CZ6 # GSG-IP4220CZ6
# #
DEF GSG-IP4220CZ6 U 0 40 Y Y 1 F N DEF GSG-IP4220CZ6 U 0 40 Y Y 1 F N
@ -795,6 +863,57 @@ X VDD 39 350 1200 300 D 50 50 1 1 W
ENDDRAW ENDDRAW
ENDDEF ENDDEF
# #
# MGA-81563
#
DEF MGA-81563 U 0 40 Y Y 1 F N
F0 "U" 0 50 60 H V C CNN
F1 "MGA-81563" 0 -50 60 H V C CNN
DRAW
S -300 300 300 -300 0 1 0 N
X GND 1 -100 -450 150 U 50 50 1 1 W
X GND 2 0 -450 150 U 50 50 1 1 W
X IN 3 100 -450 150 U 50 50 1 1 I
X GND 4 100 450 150 D 50 50 1 1 W
X GND 5 0 450 150 D 50 50 1 1 W
X OUT 6 -100 450 150 D 50 50 1 1 O
ENDDRAW
ENDDEF
#
# MOS_P
#
DEF MOS_P Q 0 40 Y N 1 F N
F0 "Q" 0 190 60 H V R CNN
F1 "MOS_P" 0 -180 60 H V R CNN
ALIAS MOSFET_P
DRAW
P 2 0 1 8 -50 -100 -50 100 N
P 2 0 1 10 0 -150 0 150 N
P 2 0 1 8 30 0 0 0 N
P 2 0 1 0 100 -100 0 -100 N
P 2 0 1 0 100 100 0 100 N
P 3 0 1 0 80 0 100 0 100 -100 N
P 5 0 1 8 30 40 30 -30 80 0 30 40 30 40 N
X D D 100 200 100 D 40 40 1 1 P
X G G -200 0 150 R 40 40 1 1 I
X S S 100 -200 100 U 40 40 1 1 P
ENDDRAW
ENDDEF
#
# NCP699
#
DEF NCP699 U 0 40 Y Y 1 F N
F0 "U" 0 200 60 H V C CNN
F1 "NCP699" 0 -200 60 H V C CNN
DRAW
S -250 250 250 -250 0 1 0 N
X VIN 1 -400 100 150 R 50 50 1 1 W
X GND 2 -400 0 150 R 50 50 1 1 W
X EN 3 -400 -100 150 R 50 50 1 1 I
X NC 4 400 -100 150 L 50 50 1 1 N
X VOUT 5 400 100 150 L 50 50 1 1 w
ENDDRAW
ENDDEF
#
# R # R
# #
DEF R R 0 0 N Y 1 F N DEF R R 0 0 N Y 1 F N
@ -813,6 +932,49 @@ X ~ 2 0 -250 100 U 60 60 1 1 P
ENDDRAW ENDDRAW
ENDDEF ENDDEF
# #
# RFFC5072
#
DEF RFFC5072 U 0 40 Y Y 1 F N
F0 "U" 0 100 60 H V C CNN
F1 "RFFC5072" 0 -100 60 H V C CNN
DRAW
S -850 850 850 -850 0 1 0 N
X EP 0 -1150 650 300 R 60 60 1 1 W
X ENBL/GPO5 1 -1150 350 300 R 50 50 1 1 B
X EXT_LO 2 -1150 250 300 R 50 50 1 1 I
X EXT_LO_DEC 3 -1150 150 300 R 50 50 1 1 P
X REXT 4 -1150 50 300 R 50 50 1 1 P
X ANA_VDD1 5 -1150 -50 300 R 50 50 1 1 W
X LFILT1 6 -1150 -150 300 R 50 50 1 1 O
X LFITLT2 7 -1150 -250 300 R 50 50 1 1 O
X LFILT3 8 -1150 -350 300 R 50 50 1 1 I
X MODE/GPO6 9 -350 -1150 300 U 50 50 1 1 B
X REF_IN 10 -250 -1150 300 U 50 50 1 1 I
X NC 20 1150 -50 300 L 50 50 1 1 N
X ENX 30 -150 1150 300 D 50 50 1 1 I
X NC 11 -150 -1150 300 U 50 50 1 1 N
X NC 21 1150 50 300 L 50 50 1 1 N
X SCLK 31 -250 1150 300 D 50 50 1 1 I
X TM 12 -50 -1150 300 U 50 50 1 1 W
X ANA_VDD2 22 1150 150 300 L 50 50 1 1 W
X SDATA 32 -350 1150 300 D 50 50 1 1 I
X NC 13 50 -1150 300 U 50 50 1 1 N
X MIX_IPP 23 1150 250 300 L 50 50 1 1 I
X NC 14 150 -1150 300 U 50 50 1 1 N
X MIX_IPN 24 1150 350 300 L 50 50 1 1 I
X GPO1/ADD1 15 250 -1150 300 U 50 50 1 1 B
X GPO3/FM 25 350 1150 300 D 50 50 1 1 B
X GPO2/ADD2 16 350 -1150 300 U 50 50 1 1 B
X GPO4/LD/DO 26 250 1150 300 D 50 50 1 1 B
X NC 17 1150 -350 300 L 50 50 1 1 N
X MIX_OPN 27 150 1150 300 D 50 50 1 1 O
X NC 18 1150 -250 300 L 50 50 1 1 N
X MIX_OPP 28 50 1150 300 D 50 50 1 1 O
X DIG_VDD 19 1150 -150 300 L 50 50 1 1 W
X RESETX 29 -50 1150 300 D 50 50 1 1 I
ENDDRAW
ENDDEF
#
# SI5351C # SI5351C
# #
DEF SI5351C U 0 40 Y Y 1 F N DEF SI5351C U 0 40 Y Y 1 F N
@ -844,6 +1006,41 @@ X CLK4 19 -100 800 300 D 50 50 1 1 O
ENDDRAW ENDDRAW
ENDDEF ENDDEF
# #
# SKY13317
#
DEF SKY13317 U 0 40 Y Y 1 F N
F0 "U" 0 0 60 H V C CNN
F1 "SKY13317" 0 250 60 H V C CNN
DRAW
S -250 300 250 -300 0 1 0 N
X GND 0 0 -600 300 U 50 50 1 1 W
X RFC 1 -550 150 300 R 50 50 1 1 B
X NC 2 -550 50 300 R 50 50 1 1 N
X V1 3 -550 -50 300 R 50 50 1 1 I
X RF1 4 -550 -150 300 R 50 50 1 1 B
X RF2 5 550 -150 300 L 50 50 1 1 B
X V2 6 550 -50 300 L 50 50 1 1 I
X V3 7 550 50 300 L 50 50 1 1 I
X RF3 8 550 150 300 L 50 50 1 1 B
ENDDRAW
ENDDEF
#
# SKY13350
#
DEF SKY13350 U 0 40 Y Y 1 F N
F0 "U" 0 200 60 H V C CNN
F1 "SKY13350" 0 -200 60 H V C CNN
DRAW
S -300 250 300 -250 0 1 0 N
X VCTL1 1 -450 100 150 R 50 50 1 1 I
X OUT1 2 -450 0 150 R 50 50 1 1 B
X GND 3 -450 -100 150 R 50 50 1 1 W
X OUT2 4 450 -100 150 L 50 50 1 1 B
X VCTL2 5 450 0 150 L 50 50 1 1 I
X INPUT 6 450 100 150 L 50 50 1 1 B
ENDDRAW
ENDDEF
#
# TPS62410 # TPS62410
# #
DEF TPS62410 U 0 40 Y Y 1 F N DEF TPS62410 U 0 40 Y Y 1 F N
@ -865,6 +1062,18 @@ X SW2 10 650 200 300 L 50 50 1 1 O
ENDDRAW ENDDRAW
ENDDEF ENDDEF
# #
# VAA
#
DEF VAA #PWR 0 0 Y Y 1 F N
F0 "#PWR" 0 60 30 H I C CNN
F1 "VAA" 0 110 30 H V C CNN
DRAW
X VAA 1 0 0 0 U 40 40 0 0 W N
C 0 60 20 0 1 0 N
P 4 0 1 0 0 40 0 0 0 0 0 0 N
ENDDRAW
ENDDEF
#
# VCC # VCC
# #
DEF VCC #PWR 0 0 Y Y 1 F P DEF VCC #PWR 0 0 Y Y 1 F P

12
hardware/jawbreaker/jawbreaker.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Sat Aug 25 00:58:51 2012 EESchema Schematic File Version 2 date Tue Sep 4 10:12:03 2012
LIBS:power LIBS:power
LIBS:device LIBS:device
LIBS:transistors LIBS:transistors
@ -35,9 +35,9 @@ EELAYER 25 0
EELAYER END EELAYER END
$Descr User 17000 11000 $Descr User 17000 11000
encoding utf-8 encoding utf-8
Sheet 1 3 Sheet 1 4
Title "jawbreaker" Title "jawbreaker"
Date "25 aug 2012" Date "4 sep 2012"
Rev "" Rev ""
Comp "Copyright 2012 Michael Ossmann" Comp "Copyright 2012 Michael Ossmann"
Comment1 "License: GPL v2" Comment1 "License: GPL v2"
@ -46,6 +46,12 @@ Comment3 ""
Comment4 "" Comment4 ""
$EndDescr $EndDescr
$Sheet $Sheet
S 2550 3300 1050 150
U 503BB638
F0 "frontend" 60
F1 "frontend.sch" 60
$EndSheet
$Sheet
S 2550 2850 1050 150 S 2550 2850 1050 150
U 50370666 U 50370666
F0 "baseband" 60 F0 "baseband" 60

4884
hardware/jawbreaker/mcu.sch
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File diff suppressed because it is too large Load Diff

2
hardware/kicad/hackrf.dcm
View File

@ -1,4 +1,4 @@
EESchema-DOCLIB Version 2.0 Date: Thu Aug 16 23:27:39 2012 EESchema-DOCLIB Version 2.0 Date: Mon Sep 3 16:15:50 2012
# #
$CMP GSG-DIODE-TVS-BI $CMP GSG-DIODE-TVS-BI
D Diode zener D Diode zener

15
hardware/kicad/hackrf.lib
View File

@ -1,4 +1,4 @@
EESchema-LIBRARY Version 2.3 Date: Thu Aug 16 23:27:39 2012 EESchema-LIBRARY Version 2.3 Date: Mon Sep 3 16:15:50 2012
#encoding utf-8 #encoding utf-8
# #
# BALUN # BALUN
@ -236,6 +236,19 @@ X VCC 14 600 300 300 L 50 50 1 1 W
ENDDRAW ENDDRAW
ENDDEF ENDDEF
# #
# GSG-900MHZ-F-ANTENNA
#
DEF GSG-900MHZ-F-ANTENNA J 0 40 Y Y 1 F N
F0 "J" 300 100 60 H V C CNN
F1 "GSG-900MHZ-F-ANTENNA" 250 650 60 H V C CNN
DRAW
P 4 0 1 0 -150 300 -150 550 0 550 0 300 N
P 15 0 1 0 0 550 100 550 100 200 200 200 200 550 300 550 300 200 400 200 400 550 500 550 500 200 600 200 600 550 700 550 700 100 N
X RF 1 0 0 300 U 50 50 1 1 B
X GND 2 -150 0 300 U 50 50 1 1 W
ENDDRAW
ENDDEF
#
# GSG-DIODE-TVS-BI # GSG-DIODE-TVS-BI
# #
DEF GSG-DIODE-TVS-BI D 0 40 N N 1 F N DEF GSG-DIODE-TVS-BI D 0 40 N N 1 F N

2
hardware/licorice/licorice-cache.lib
View File

@ -1,4 +1,4 @@
EESchema-LIBRARY Version 2.3 Date: Mon Aug 20 16:01:29 2012 EESchema-LIBRARY Version 2.3 Date: Mon Aug 27 11:49:57 2012
#encoding utf-8 #encoding utf-8
# #
# BALUN-B0310J50100AHF # BALUN-B0310J50100AHF

1168
hardware/licorice/licorice.brd
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File diff suppressed because it is too large Load Diff

16
hardware/licorice/licorice.cmp
View File

@ -1,4 +1,4 @@
Cmp-Mod V01 Created by CvPCB (2011-06-30 BZR 3033)-stable date = Mon Aug 20 15:47:31 2012 Cmp-Mod V01 Created by CvPCB (2011-06-30 BZR 3033)-stable date = Mon Aug 27 11:49:46 2012
BeginCmp BeginCmp
TimeStamp = /4FAECB99; TimeStamp = /4FAECB99;
@ -476,6 +476,20 @@ ValeurCmp = 47pF;
IdModule = GSG-0402; IdModule = GSG-0402;
EndCmp EndCmp
BeginCmp
TimeStamp = /503BB2BD;
Reference = C69;
ValeurCmp = 10nF;
IdModule = GSG-0402;
EndCmp
BeginCmp
TimeStamp = /503BB2CE;
Reference = C70;
ValeurCmp = 10nF;
IdModule = GSG-0402;
EndCmp
BeginCmp BeginCmp
TimeStamp = /4FB3F9B0; TimeStamp = /4FB3F9B0;
Reference = D1; Reference = D1;

238
hardware/licorice/licorice.net
View File

@ -1,4 +1,4 @@
# EESchema Netlist Version 1.1 created Mon Aug 20 15:47:31 2012 # EESchema Netlist Version 1.1 created Mon Aug 27 11:49:46 2012
( (
( /4FAECB99 GSG-0402 C1 33pF ( /4FAECB99 GSG-0402 C1 33pF
( 1 VCC ) ( 1 VCC )
@ -29,8 +29,8 @@
( 2 /MIX_BYPASS ) ( 2 /MIX_BYPASS )
) )
( /501EF782 GSG-0402 C8 47pF ( /501EF782 GSG-0402 C8 47pF
( 1 N-000054 ) ( 1 N-000050 )
( 2 N-000020 ) ( 2 N-000041 )
) )
( /502B53A4 GSG-0402 C9 10nF ( /502B53A4 GSG-0402 C9 10nF
( 1 N-000015 ) ( 1 N-000015 )
@ -45,68 +45,68 @@
( 2 /LP ) ( 2 /LP )
) )
( /4FAEC84D GSG-0402 C12 330pF ( /4FAEC84D GSG-0402 C12 330pF
( 1 N-000059 ) ( 1 N-000055 )
( 2 GND ) ( 2 GND )
) )
( /4FAEC853 GSG-0402 C13 330pF ( /4FAEC853 GSG-0402 C13 330pF
( 1 N-000048 ) ( 1 N-000046 )
( 2 GND ) ( 2 GND )
) )
( /4FAEC8AD GSG-0402 C14 8p2 ( /4FAEC8AD GSG-0402 C14 8p2
( 1 N-000049 ) ( 1 N-000045 )
( 2 N-000051 ) ( 2 N-000086 )
) )
( /4FAEC8B0 GSG-0402 C15 180pF ( /4FAEC8B0 GSG-0402 C15 180pF
( 1 N-000049 ) ( 1 N-000045 )
( 2 N-000050 ) ( 2 N-000047 )
) )
( /501F4793 GSG-0402 C16 33pF ( /501F4793 GSG-0402 C16 33pF
( 1 /!MIX_BYPASS ) ( 1 /!MIX_BYPASS )
( 2 GND ) ( 2 GND )
) )
( /501F41BB GSG-0402 C17 10nF ( /501F41BB GSG-0402 C17 10nF
( 1 N-000056 ) ( 1 N-000052 )
( 2 N-000073 ) ( 2 N-000071 )
) )
( /501F41B9 GSG-0402 C18 10nF ( /501F41B9 GSG-0402 C18 10nF
( 1 N-000017 ) ( 1 N-000020 )
( 2 N-000057 ) ( 2 N-000053 )
) )
( /502E6F8B GSG-0402 C19 33pF ( /502E6F8B GSG-0402 C19 33pF
( 1 GND ) ( 1 GND )
( 2 /LP ) ( 2 /LP )
) )
( /501F41BD GSG-0402 C20 10nF ( /501F41BD GSG-0402 C20 10nF
( 1 N-000072 ) ( 1 N-000070 )
( 2 N-000001 ) ( 2 N-000003 )
) )
( /501EF768 GSG-0402 C21 47pF ( /501EF768 GSG-0402 C21 47pF
( 1 N-000019 ) ( 1 N-000069 )
( 2 N-000044 ) ( 2 N-000068 )
) )
( /502B4779 GSG-0402 C22 33pF ( /502B4779 GSG-0402 C22 33pF
( 1 GND ) ( 1 GND )
( 2 /RX ) ( 2 /RX )
) )
( /502B4C6F GSG-0402 C23 10nF ( /502B4C6F GSG-0402 C23 10nF
( 1 N-000013 ) ( 1 N-000014 )
( 2 N-000086 ) ( 2 N-000088 )
) )
( /502E6F11 GSG-0402 C24 33pF ( /502E6F11 GSG-0402 C24 33pF
( 1 GND ) ( 1 GND )
( 2 /TX ) ( 2 /TX )
) )
( /4FAA149B GSG-0402 C25 47pF ( /4FAA149B GSG-0402 C25 47pF
( 1 N-000060 ) ( 1 N-000056 )
( 2 N-000022 ) ( 2 N-000019 )
) )
( /501EF311 GSG-0402 C26 47pF ( /501EF311 GSG-0402 C26 47pF
( 1 N-000075 ) ( 1 N-000073 )
( 2 N-000074 ) ( 2 N-000072 )
) )
( /502B477A GSG-0402 C27 10nF ( /502B477A GSG-0402 C27 10nF
( 1 N-000069 ) ( 1 N-000075 )
( 2 N-000007 ) ( 2 N-000006 )
) )
( /502E6FEE GSG-0402 C28 33pF ( /502E6FEE GSG-0402 C28 33pF
( 1 /HP ) ( 1 /HP )
@ -117,12 +117,12 @@
( 2 GND ) ( 2 GND )
) )
( /502B56C2 GSG-0402 C30 10nF ( /502B56C2 GSG-0402 C30 10nF
( 1 N-000009 ) ( 1 N-000008 )
( 2 N-000021 ) ( 2 N-000018 )
) )
( /502B571F GSG-0402 C31 47pF ( /502B571F GSG-0402 C31 47pF
( 1 N-000018 ) ( 1 N-000017 )
( 2 N-000010 ) ( 2 N-000009 )
) )
( /502B4780 GSG-0402 C32 33pF ( /502B4780 GSG-0402 C32 33pF
( 1 /TX ) ( 1 /TX )
@ -166,11 +166,11 @@
) )
( /502B5738 GSG-0402 C42 47pF ( /502B5738 GSG-0402 C42 47pF
( 1 N-000012 ) ( 1 N-000012 )
( 2 N-000087 ) ( 2 N-000089 )
) )
( /501F4169 GSG-0402 C43 10nF ( /501F4169 GSG-0402 C43 10nF
( 1 N-000088 ) ( 1 N-000090 )
( 2 N-000008 ) ( 2 N-000011 )
) )
( /502E6ECB GSG-0402 C44 33pF ( /502E6ECB GSG-0402 C44 33pF
( 1 GND ) ( 1 GND )
@ -178,30 +178,30 @@
) )
( /502B4C15 GSG-0402 C45 10nF ( /502B4C15 GSG-0402 C45 10nF
( 1 N-000004 ) ( 1 N-000004 )
( 2 N-000068 ) ( 2 N-000064 )
) )
( /501F477D GSG-0402 C46 33pF ( /501F477D GSG-0402 C46 33pF
( 1 GND ) ( 1 GND )
( 2 /!MIX_BYPASS ) ( 2 /!MIX_BYPASS )
) )
( /501EF6BA GSG-0402 C47 47pF ( /501EF6BA GSG-0402 C47 47pF
( 1 N-000014 ) ( 1 N-000065 )
( 2 N-000055 ) ( 2 N-000051 )
) )
( /502E5F58 GSG-0402 C48 100pF ( /502E5F58 GSG-0402 C48 100pF
( 1 N-000102 ) ( 1 N-000104 )
( 2 /RX_AMP_OUT ) ( 2 /RX_AMP_OUT )
) )
( /501EF6A1 GSG-0402 C49 47pF ( /501EF6A1 GSG-0402 C49 47pF
( 1 N-000071 ) ( 1 N-000067 )
( 2 N-000070 ) ( 2 N-000066 )
) )
( /502C6D36 GSG-0402 C50 100pF ( /502C6D36 GSG-0402 C50 100pF
( 1 N-000039 ) ( 1 N-000043 )
( 2 GND ) ( 2 GND )
) )
( /502C6DB4 GSG-0402 C51 1uF ( /502C6DB4 GSG-0402 C51 1uF
( 1 N-000039 ) ( 1 N-000043 )
( 2 GND ) ( 2 GND )
) )
( /502E6EB0 GSG-0402 C52 33pF ( /502E6EB0 GSG-0402 C52 33pF
@ -222,10 +222,10 @@
) )
( /502E5F55 GSG-0402 C56 100pF ( /502E5F55 GSG-0402 C56 100pF
( 1 /TX_AMP_OUT ) ( 1 /TX_AMP_OUT )
( 2 N-000102 ) ( 2 N-000104 )
) )
( /502E665E GSG-0402 C57 100pF ( /502E665E GSG-0402 C57 100pF
( 1 N-000089 ) ( 1 N-000091 )
( 2 /TX_AMP_IN ) ( 2 /TX_AMP_IN )
) )
( /502E79FA GSG-0402 C58 33pF ( /502E79FA GSG-0402 C58 33pF
@ -233,20 +233,20 @@
( 2 /AMP_BYPASS ) ( 2 /AMP_BYPASS )
) )
( /502E6909 GSG-0402 C59 10nF ( /502E6909 GSG-0402 C59 10nF
( 1 N-000043 ) ( 1 N-000040 )
( 2 N-000041 ) ( 2 N-000030 )
) )
( /502E6667 GSG-0402 C60 100pF ( /502E6667 GSG-0402 C60 100pF
( 1 /RX_AMP_IN ) ( 1 /RX_AMP_IN )
( 2 N-000089 ) ( 2 N-000091 )
) )
( /502E79CE GSG-0402 C61 33pF ( /502E79CE GSG-0402 C61 33pF
( 1 /TX_AMP ) ( 1 /TX_AMP )
( 2 GND ) ( 2 GND )
) )
( /502C6D4A GSG-0402 C62 10nF ( /502C6D4A GSG-0402 C62 10nF
( 1 N-000046 ) ( 1 N-000042 )
( 2 N-000094 ) ( 2 N-000098 )
) )
( /502E7989 GSG-0402 C63 33pF ( /502E7989 GSG-0402 C63 33pF
( 1 GND ) ( 1 GND )
@ -272,32 +272,40 @@
( 1 /REF_IN ) ( 1 /REF_IN )
( 2 GND ) ( 2 GND )
) )
( /503BB2BD GSG-0402 C69 10nF
( 1 N-000074 )
( 2 GND )
)
( /503BB2CE GSG-0402 C70 10nF
( 1 GND )
( 2 N-000099 )
)
( /4FB3F9B0 GSG-0402 D1 GSG-DIODE-TVS-BI ( /4FB3F9B0 GSG-0402 D1 GSG-DIODE-TVS-BI
( 1 GND ) ( 1 GND )
( 2 N-000094 ) ( 2 N-000098 )
) )
( /502AFA8C GSG-0402 L1 DNP ( /502AFA8C GSG-0402 L1 DNP
( 1 N-000095 ) ( 1 N-000095 )
( 2 N-000096 ) ( 2 N-000096 )
) )
( /502B4BB2 GSG-0603 L2 180nH ( /502B4BB2 GSG-0603 L2 180nH
( 1 N-000003 ) ( 1 N-000001 )
( 2 VCC ) ( 2 VCC )
) )
( /502B4BB6 GSG-0603 L3 180nH ( /502B4BB6 GSG-0603 L3 180nH
( 1 N-000067 ) ( 1 N-000063 )
( 2 VCC ) ( 2 VCC )
) )
( /4FB55E30 GSG-0402 L4 DNP ( /4FB55E30 GSG-0402 L4 DNP
( 1 N-000067 ) ( 1 N-000063 )
( 2 N-000003 ) ( 2 N-000001 )
) )
( /502C6D12 GSG-0603 L5 180nH ( /502C6D12 GSG-0603 L5 180nH
( 1 N-000039 ) ( 1 N-000043 )
( 2 N-000102 ) ( 2 N-000104 )
) )
( /4FA9C5A4 GSG-SMA-EDGE P1 TX-IN ( /4FA9C5A4 GSG-SMA-EDGE P1 TX-IN
( 1 N-000054 ) ( 1 N-000050 )
( 2 GND ) ( 2 GND )
( 3 GND ) ( 3 GND )
( 4 GND ) ( 4 GND )
@ -316,14 +324,14 @@
( 10 GND ) ( 10 GND )
) )
( /4FA9C5BB GSG-SMA-EDGE P3 RX-OUT ( /4FA9C5BB GSG-SMA-EDGE P3 RX-OUT
( 1 N-000055 ) ( 1 N-000051 )
( 2 GND ) ( 2 GND )
( 3 GND ) ( 3 GND )
( 4 GND ) ( 4 GND )
( 5 GND ) ( 5 GND )
) )
( /4F94D0F2 GSG-SMA-EDGE P4 ANTENNA ( /4F94D0F2 GSG-SMA-EDGE P4 ANTENNA
( 1 N-000094 ) ( 1 N-000098 )
( 2 GND ) ( 2 GND )
( 3 GND ) ( 3 GND )
( 4 GND ) ( 4 GND )
@ -378,25 +386,25 @@
( 1 ? ) ( 1 ? )
) )
( /502E69D1 SOT23GDS Q1 MOSFET_P ( /502E69D1 SOT23GDS Q1 MOSFET_P
( D N-000092 ) ( D N-000093 )
( G /!AMP_PWR ) ( G /!AMP_PWR )
( S VCC ) ( S VCC )
) )
( /4FAEC850 GSG-0402 R1 470 ( /4FAEC850 GSG-0402 R1 470
( 1 N-000048 ) ( 1 N-000046 )
( 2 N-000059 ) ( 2 N-000055 )
) )
( /4FAEC856 GSG-0402 R2 470 ( /4FAEC856 GSG-0402 R2 470
( 1 N-000049 ) ( 1 N-000045 )
( 2 N-000048 ) ( 2 N-000046 )
) )
( /4FAEC8B2 GSG-0402 R3 22k ( /4FAEC8B2 GSG-0402 R3 22k
( 1 N-000051 ) ( 1 N-000086 )
( 2 N-000050 ) ( 2 N-000047 )
) )
( /4FAECC79 GSG-0402 R4 51k ( /4FAECC79 GSG-0402 R4 51k
( 1 GND ) ( 1 GND )
( 2 N-000047 ) ( 2 N-000044 )
) )
( /4FAECE50 GSG-0402 R5 4k7 ( /4FAECE50 GSG-0402 R5 4k7
( 1 VCC ) ( 1 VCC )
@ -407,53 +415,53 @@
( 2 /ENX ) ( 2 /ENX )
) )
( /5032B025 GSG-0402 R7 33 ( /5032B025 GSG-0402 R7 33
( 1 N-000092 ) ( 1 N-000093 )
( 2 N-000039 ) ( 2 N-000043 )
) )
( /501EF483 GSG-B0310J50100AHF T1 MIX_IN_BALUN ( /501EF483 GSG-B0310J50100AHF T1 MIX_IN_BALUN
( 1 N-000069 ) ( 1 N-000075 )
( 2 GND ) ( 2 N-000074 )
( 3 N-000096 ) ( 3 N-000096 )
( 4 N-000095 ) ( 4 N-000095 )
) )
( /501EF4A4 GSG-B0310J50100AHF T2 MIX_OUT_BALUN ( /501EF4A4 GSG-B0310J50100AHF T2 MIX_OUT_BALUN
( 1 N-000068 ) ( 1 N-000064 )
( 2 GND ) ( 2 N-000099 )
( 3 N-000067 ) ( 3 N-000063 )
( 4 N-000003 ) ( 4 N-000001 )
) )
( /501EF778 GSG-SKY13350-385LF U1 SKY13350 ( /501EF778 GSG-SKY13350-385LF U1 SKY13350
( 1 /!MIX_BYPASS ) ( 1 /!MIX_BYPASS )
( 2 N-000019 ) ( 2 N-000069 )
( 3 GND ) ( 3 GND )
( 4 N-000018 ) ( 4 N-000017 )
( 5 /MIX_BYPASS ) ( 5 /MIX_BYPASS )
( 6 N-000020 ) ( 6 N-000041 )
) )
( /502B490F GSG-SKY13350-385LF U2 SKY13350 ( /502B490F GSG-SKY13350-385LF U2 SKY13350
( 1 /RX ) ( 1 /RX )
( 2 N-000002 ) ( 2 N-000002 )
( 3 GND ) ( 3 GND )
( 4 N-000086 ) ( 4 N-000088 )
( 5 /TX ) ( 5 /TX )
( 6 N-000001 ) ( 6 N-000003 )
) )
( /4F94D561 GSG-LP0603 U3 RX_LOWPASS_FILTER ( /4F94D561 GSG-LP0603 U3 RX_LOWPASS_FILTER
( 1 N-000057 ) ( 1 N-000053 )
( 2 GND ) ( 2 GND )
( 3 GND ) ( 3 GND )
( 4 N-000056 ) ( 4 N-000052 )
) )
( /502BE21C GSG-QFN32 U4 RFFC5072 ( /502BE21C GSG-QFN32 U4 RFFC5072
( 0 GND ) ( 0 GND )
( 1 /GPO5 ) ( 1 /GPO5 )
( 2 ? ) ( 2 ? )
( 3 ? ) ( 3 ? )
( 4 N-000047 ) ( 4 N-000044 )
( 5 VCC ) ( 5 VCC )
( 6 N-000051 ) ( 6 N-000086 )
( 7 N-000049 ) ( 7 N-000045 )
( 8 N-000059 ) ( 8 N-000055 )
( 9 /GPO6 ) ( 9 /GPO6 )
( 10 /REF_IN ) ( 10 /REF_IN )
( 11 ? ) ( 11 ? )
@ -472,8 +480,8 @@
( 24 N-000096 ) ( 24 N-000096 )
( 25 /GPO3 ) ( 25 /GPO3 )
( 26 /GPO4 ) ( 26 /GPO4 )
( 27 N-000003 ) ( 27 N-000001 )
( 28 N-000067 ) ( 28 N-000063 )
( 29 /RESETX ) ( 29 /RESETX )
( 30 /ENX ) ( 30 /ENX )
( 31 /SCLK ) ( 31 /SCLK )
@ -481,67 +489,67 @@
) )
( /501F3B20 GSG-SKY13350-385LF U5 SKY13350 ( /501F3B20 GSG-SKY13350-385LF U5 SKY13350
( 1 /LP ) ( 1 /LP )
( 2 N-000017 ) ( 2 N-000020 )
( 3 GND ) ( 3 GND )
( 4 N-000022 ) ( 4 N-000019 )
( 5 /HP ) ( 5 /HP )
( 6 N-000021 ) ( 6 N-000018 )
) )
( /501EF258 GSG-SKY13350-385LF U6 SKY13350 ( /501EF258 GSG-SKY13350-385LF U6 SKY13350
( 1 /HP ) ( 1 /HP )
( 2 N-000074 ) ( 2 N-000072 )
( 3 GND ) ( 3 GND )
( 4 N-000073 ) ( 4 N-000071 )
( 5 /LP ) ( 5 /LP )
( 6 N-000072 ) ( 6 N-000070 )
) )
( /502B477E GSG-SKY13350-385LF U7 SKY13350 ( /502B477E GSG-SKY13350-385LF U7 SKY13350
( 1 /RX ) ( 1 /RX )
( 2 N-000015 ) ( 2 N-000015 )
( 3 GND ) ( 3 GND )
( 4 N-000044 ) ( 4 N-000068 )
( 5 /TX ) ( 5 /TX )
( 6 N-000007 ) ( 6 N-000006 )
) )
( /4F94D4F4 GSG-HP-DEA U8 RX_HIGHPASS_FILTER ( /4F94D4F4 GSG-HP-DEA U8 RX_HIGHPASS_FILTER
( 1 N-000075 ) ( 1 N-000073 )
( 2 GND ) ( 2 GND )
( 3 N-000060 ) ( 3 N-000056 )
( 4 GND ) ( 4 GND )
) )
( /502B5704 GSG-SKY13317-373LF U9 SKY13317 ( /502B5704 GSG-SKY13317-373LF U9 SKY13317
( 0 GND ) ( 0 GND )
( 1 N-000008 ) ( 1 N-000011 )
( 2 ? ) ( 2 ? )
( 3 /TX_MIX_BP ) ( 3 /TX_MIX_BP )
( 4 N-000010 ) ( 4 N-000009 )
( 5 N-000009 ) ( 5 N-000008 )
( 6 /!MIX_BYPASS ) ( 6 /!MIX_BYPASS )
( 7 /RX_MIX_BP ) ( 7 /RX_MIX_BP )
( 8 N-000012 ) ( 8 N-000012 )
) )
( /502B4C1C GSG-SKY13350-385LF U10 SKY13350 ( /502B4C1C GSG-SKY13350-385LF U10 SKY13350
( 1 /RX ) ( 1 /RX )
( 2 N-000070 ) ( 2 N-000066 )
( 3 GND ) ( 3 GND )
( 4 N-000013 ) ( 4 N-000014 )
( 5 /TX ) ( 5 /TX )
( 6 N-000004 ) ( 6 N-000004 )
) )
( /501EF646 GSG-SKY13350-385LF U11 SKY13350 ( /501EF646 GSG-SKY13350-385LF U11 SKY13350
( 1 /MIX_BYPASS ) ( 1 /MIX_BYPASS )
( 2 N-000087 ) ( 2 N-000089 )
( 3 GND ) ( 3 GND )
( 4 N-000071 ) ( 4 N-000067 )
( 5 /!MIX_BYPASS ) ( 5 /!MIX_BYPASS )
( 6 N-000014 ) ( 6 N-000065 )
) )
( /502C6BDF GSG-SKY13317-373LF U12 SKY13317 ( /502C6BDF GSG-SKY13317-373LF U12 SKY13317
( 0 GND ) ( 0 GND )
( 1 N-000088 ) ( 1 N-000090 )
( 2 ? ) ( 2 ? )
( 3 /AMP_BYPASS ) ( 3 /AMP_BYPASS )
( 4 N-000041 ) ( 4 N-000030 )
( 5 /TX_AMP_IN ) ( 5 /TX_AMP_IN )
( 6 /TX_AMP ) ( 6 /TX_AMP )
( 7 /RX_AMP ) ( 7 /RX_AMP )
@ -550,21 +558,21 @@
( /502DE480 GSG-SOT363 U13 MGA-81563 ( /502DE480 GSG-SOT363 U13 MGA-81563
( 1 GND ) ( 1 GND )
( 2 GND ) ( 2 GND )
( 3 N-000089 ) ( 3 N-000091 )
( 4 GND ) ( 4 GND )
( 5 GND ) ( 5 GND )
( 6 N-000102 ) ( 6 N-000104 )
) )
( /502C6BE2 GSG-SKY13317-373LF U14 SKY13317 ( /502C6BE2 GSG-SKY13317-373LF U14 SKY13317
( 0 GND ) ( 0 GND )
( 1 N-000046 ) ( 1 N-000042 )
( 2 ? ) ( 2 ? )
( 3 /TX_AMP ) ( 3 /TX_AMP )
( 4 /TX_AMP_OUT ) ( 4 /TX_AMP_OUT )
( 5 /RX_AMP_IN ) ( 5 /RX_AMP_IN )
( 6 /RX_AMP ) ( 6 /RX_AMP )
( 7 /AMP_BYPASS ) ( 7 /AMP_BYPASS )
( 8 N-000043 ) ( 8 N-000040 )
) )
( /4FB2F586 GSG-S-PVQFN-14 U15 GSG-74HC04 ( /4FB2F586 GSG-S-PVQFN-14 U15 GSG-74HC04
( 0 GND ) ( 0 GND )
@ -943,6 +951,16 @@ $component C68
C? C?
C1-1 C1-1
$endlist $endlist
$component C69
SM*
C?
C1-1
$endlist
$component C70
SM*
C?
C1-1
$endlist
$component D1 $component D1
D? D?
SO* SO*

464
hardware/licorice/licorice.sch
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