diff --git a/firmware/common/max2837_regs.def b/firmware/common/max2837_regs.def
index 75cf8f1a..96291866 100644
--- a/firmware/common/max2837_regs.def
+++ b/firmware/common/max2837_regs.def
@@ -16,7 +16,7 @@
 /* n=name, r=regnum, o=offset (bits from LSB), l=length (bits) */
 #define __MREG__(n,r,o,l) \
 static inline uint16_t get_##n(void) { \
-        return (max2837_regs[r] >> o) & ((1<<l)-1); \
+	return (max2837_regs[r] >> (o-l+1)) & ((1<<l)-1);	\
 } \
 static inline void set_##n(uint16_t v) {      \
 	max2837_regs[r] &= ~(((1<<l)-1)<<(o-l+1));  \
diff --git a/firmware/common/rffc5071.c b/firmware/common/rffc5071.c
index 6b2e398c..768c3104 100644
--- a/firmware/common/rffc5071.c
+++ b/firmware/common/rffc5071.c
@@ -19,16 +19,86 @@
  * Boston, MA 02110-1301, USA.
  */
 
+/*
+ * 'gcc -DTEST -DDEBUG -O2 -o test rffc5071.c' prints out what test
+ * program would do if it had a real spi library
+ */
+
 #include <stdint.h>
+#include <string.h>
+#include "rffc5071.h"
+#include "rffc5071_regs.def" // private register def macros
+
+#if (defined DEBUG)
+#include <stdio.h>
+#define LOG printf
+#else
+#define LOG(x,...)
 #include <libopencm3/lpc43xx/ssp.h>
 #include <libopencm3/lpc43xx/scu.h>
 #include <libopencm3/lpc43xx/gpio.h>
 #include "hackrf_core.h"
-#include "rffc5071.h"
+#endif
 
-/* Set up pins for bit-banged serial interface. */
+/* Default register values. */
+static uint16_t rffc5071_regs_default[RFFC5071_NUM_REGS] = { 
+	0xbefa,   /* 00 */
+	0x4064,   /* 01 */
+	0x9055,   /* 02 */
+	0x2d02,   /* 03 */
+	0xacbf,   /* 04 */
+	0xacbf,   /* 05 */
+	0x0028,   /* 06 */
+	0x0028,   /* 07 */
+	0xff00,   /* 08 */
+	0x8220,   /* 09 */
+	0x0202,   /* 0A */
+	0x4800,   /* 0B */
+	0x1a94,   /* 0C */
+	0xd89d,   /* 0D */
+	0x8900,   /* 0E */
+	0x1e84,   /* 0F */
+	0x89d8,   /* 10 */
+	0x9d00,   /* 11 */
+	0x2a20,   /* 12 */
+	0x0000,   /* 13 */
+	0x0000,   /* 14 */
+	0x0000,   /* 15 */
+	0x0000,   /* 16 */
+	0x4900,   /* 17 */
+	0x0281,   /* 18 */
+	0xf00f,   /* 19 */
+	0x0000,   /* 1A */
+	0x0000,   /* 1B */
+	0xc840,   /* 1C */
+	0x1000,   /* 1D */
+	0x0005,   /* 1E */ };
+
+uint16_t rffc5071_regs[RFFC5071_NUM_REGS];
+
+/* Mark all regsisters dirty so all will be written at init. */
+uint32_t rffc5071_regs_dirty = 0x7fffffff;
+
+/* Set up all registers according to defaults specified in docs. */
 void rffc5071_init(void)
 {
+	LOG("# rffc5071_init\n");
+	memcpy(rffc5071_regs, rffc5071_regs_default, sizeof(rffc5071_regs));
+	rffc5071_regs_dirty = 0x7fffffff;
+
+	/* Write default register values to chip. */
+	rffc5071_regs_commit();
+}
+
+/*
+ * Set up pins for GPIO and SPI control, configure SSP peripheral for SPI, and
+ * set our own default register configuration.
+ */
+void rffc5071_setup(void)
+{
+	rffc5071_init();
+	LOG("# rffc5071_setup\n");
+#if !defined TEST
 	/* Configure GPIO pins. */
 	scu_pinmux(SCU_MIXER_ENX, SCU_GPIO_FAST);
 	scu_pinmux(SCU_MIXER_SCLK, SCU_GPIO_FAST);
@@ -40,68 +110,52 @@ void rffc5071_init(void)
 	/* set to known state */
 	gpio_set(PORT_MIXER, PIN_MIXER_ENX); /* active low */
 	gpio_clear(PORT_MIXER, (PIN_MIXER_SCLK | PIN_MIXER_SDATA));
+#endif
 
-	//FIXME hard coded setup, fields not broken out
 	/* initial setup */
-	rffc5071_reg_write(RFFC5071_P2_FREQ1, 0x0000);
-	rffc5071_reg_write(RFFC5071_VCO_AUTO, 0xff00);
-	rffc5071_reg_write(RFFC5071_CT_CAL1, 0xacbf);
-	rffc5071_reg_write(RFFC5071_CT_CAL2, 0xacbf);
-	rffc5071_reg_write(RFFC5071_TEST, 0x0005);
+	/* put zeros in freq contol registers */
+	set_RFFC5071_P2N(0);
+	set_RFFC5071_P2LODIV(0);
+	set_RFFC5071_P2PRESC(0);
+	set_RFFC5071_P2VCOSEL(0);
 
-	/* set to be configured via 3-wire interface, not control pins */
-	rffc5071_reg_write(RFFC5071_SDI_CTRL, 0x8000);
+	set_RFFC5071_P2N(0);
+	set_RFFC5071_P2LODIV(0);
+	set_RFFC5071_P2PRESC(0);
+	set_RFFC5071_P2VCOSEL(0);
 
-	//rffc5071_reg_write(MIX_CONT, 0xc800); /* full duplex */
-	rffc5071_reg_write(RFFC5071_MIX_CONT, 0x4800); /* half duplex */
-}
+	set_RFFC5071_P2N(0);
+	set_RFFC5071_P2LODIV(0);
+	set_RFFC5071_P2PRESC(0);
+	set_RFFC5071_P2VCOSEL(0);
 
-#define LO_MAX   5400
-#define REF_FREQ 50
+	/* set ENBL and MODE to be configured via 3-wire interface,
+	 * not control pins. */
+	set_RFFC5071_SIPIN(1);
 
-/* configure frequency synthesizer in integer mode (lo in MHz) */
-void rffc5071_config_synth_int(uint16_t lo) {
-	uint8_t n_lo;
-	uint8_t lodiv;
-	uint16_t fvco;
-	uint8_t fbkdiv;
-	uint16_t n;
+	/* Initial settings for Lollipop switches, same for both
+	 * paths. These could use some #defines that iron out the
+	 * (non)inverted signals.
+	 *
+	 * bit0: SWTXB1 (!tx_bypass)
+	 * bit1: SWRXB1 (rx_bypass)
+	 * bit2: SWTXA1 (tx_hp)
+	 * bit3: unused (lock bit)
+	 * bit4: SWRXA1 (rx_hp)
+	 * bit5 SWD1 (!tx_ant)
+	 *
+	 * Unknown whether shift is needed. There are 7 register bits
+	 * to hold 6 GPO bits. */
+	set_RFFC5071_P1GPO(0b010100<<1);
+	set_RFFC5071_P2GPO(0b010100<<1);
 
-	/* n_lo = int(log2(LO_MAX/lo)) */
-	for (n_lo = 0; n_lo < 5; n_lo++)
-		if ((2 << n_lo) > (LO_MAX / lo))
-			break;
+	/* send lock flag on GPO4 */
+	set_RFFC5071_LOCK(1);
 
-	lodiv = 1 << n_lo;
-	fvco = lodiv * lo;
+	/* GPOs are active at all times */
+	set_RFFC5071_GATE(1);
 
-	if (fvco > 3200) {
-		fbkdiv = 4;
-		/* set charge pump for VCO > 3.2 GHz */
-		rffc5071_reg_write(RFFC5071_LF, 0xbefb);
-	} else {
-		fbkdiv = 2;
-	}
-
-	n = (fvco / fbkdiv) / REF_FREQ;
-
-	rffc5071_reg_write(RFFC5071_P1_FREQ1,
-			(n << 7) | (n_lo << 4) | (fbkdiv << 1));
-	rffc5071_reg_write(RFFC5071_P1_FREQ2, 0x0000);
-	rffc5071_reg_write(RFFC5071_P1_FREQ3, 0x0000);
-
-	rffc5071_reg_write(RFFC5071_P2_FREQ1,
-			(n << 7) | (n_lo << 4) | (fbkdiv << 1));
-	rffc5071_reg_write(RFFC5071_P2_FREQ2, 0x0000);
-	rffc5071_reg_write(RFFC5071_P2_FREQ3, 0x0000);
-}
-
-void rffc5071_enable_tx(void) {
-	rffc5071_reg_write(RFFC5071_SDI_CTRL, 0xc000); /* mixer 1 (TX) */
-}
-
-void rffc5071_enable_rx(void) {
-	rffc5071_reg_write(RFFC5071_SDI_CTRL, 0xe000); /* mixer 2 (RX) */
+	rffc5071_regs_commit();
 }
 
 void serial_delay(void)
@@ -112,73 +166,24 @@ void serial_delay(void)
 		__asm__("nop");
 }
 
-/*
- * Send 25 bits:
- *   first bit is ignored,
- *   second bit is zero for write operation,
- *   next 7 bits are register address,
- *   next 16 bits are register value.
- */
-void rffc5071_reg_write(uint8_t reg, uint16_t val)
-{
-	int bits = 25;
-	int msb = 1 << (bits -1);
-	uint32_t data = ((reg & 0x7f) << 16) | val;
-
-	/* make sure everything is starting in the correct state */
-	gpio_set(PORT_MIXER, PIN_MIXER_ENX);
-	gpio_clear(PORT_MIXER, (PIN_MIXER_SCLK | PIN_MIXER_SDATA));
-
-	/*
-	 * The device requires two clocks while ENX is high before a serial
-	 * transaction.  This is not clearly documented.
-	 */
-	serial_delay();
-	gpio_set(PORT_MIXER, PIN_MIXER_SCLK);
-
-	serial_delay();
-	gpio_clear(PORT_MIXER, PIN_MIXER_SCLK);
-
-	serial_delay();
-	gpio_set(PORT_MIXER, PIN_MIXER_SCLK);
-
-	serial_delay();
-	gpio_clear(PORT_MIXER, PIN_MIXER_SCLK);
-
-	/* start transaction by bringing ENX low */
-	gpio_clear(PORT_MIXER, PIN_MIXER_ENX);
-
-	while (bits--) {
-		if (data & msb)
-			gpio_set(PORT_MIXER, PIN_MIXER_SDATA);
-		else
-			gpio_clear(PORT_MIXER, PIN_MIXER_SDATA);
-		data <<= 1;
-
-		serial_delay();
-		gpio_set(PORT_MIXER, PIN_MIXER_SCLK);
-
-		serial_delay();
-		gpio_clear(PORT_MIXER, PIN_MIXER_SCLK);
-	}
-
-	serial_delay();
-	gpio_set(PORT_MIXER, PIN_MIXER_ENX);
-}
-
-/*
+/* SPI register read.
+ *
  * Send 9 bits:
  *   first bit is ignored,
  *   second bit is one for read operation,
  *   next 7 bits are register address.
  * Then receive 16 bits (register value).
  */
-uint16_t rffc5071_reg_read(uint8_t reg)
-{
+uint16_t rffc5071_spi_read(uint8_t r) {
+
 	int bits = 9;
 	int msb = 1 << (bits -1);
-	uint32_t data = 0x80 | (reg & 0x7f);
+	uint32_t data = 0x80 | (r & 0x7f);
 
+#if DEBUG
+	LOG("reg%d = 0\n", r);
+	return 0;
+#else
 	/* make sure everything is starting in the correct state */
 	gpio_set(PORT_MIXER, PIN_MIXER_ENX);
 	gpio_clear(PORT_MIXER, (PIN_MIXER_SCLK | PIN_MIXER_SDATA));
@@ -245,4 +250,236 @@ uint16_t rffc5071_reg_read(uint8_t reg)
 	gpio_set(PORT_MIXER, PIN_MIXER_ENX);
 
 	return data;
+#endif /* DEBUG */
 }
+
+/* SPI register write
+ *
+ * Send 25 bits:
+ *   first bit is ignored,
+ *   second bit is zero for write operation,
+ *   next 7 bits are register address,
+ *   next 16 bits are register value.
+ */
+void rffc5071_spi_write(uint8_t r, uint16_t v) {
+
+#if DEBUG
+	LOG("0x%04x -> reg%d\n", v, r);
+#else
+
+	int bits = 25;
+	int msb = 1 << (bits -1);
+	uint32_t data = ((reg & 0x7f) << 16) | val;
+
+	/* make sure everything is starting in the correct state */
+	gpio_set(PORT_MIXER, PIN_MIXER_ENX);
+	gpio_clear(PORT_MIXER, (PIN_MIXER_SCLK | PIN_MIXER_SDATA));
+
+	/*
+	 * The device requires two clocks while ENX is high before a serial
+	 * transaction.  This is not clearly documented.
+	 */
+	serial_delay();
+	gpio_set(PORT_MIXER, PIN_MIXER_SCLK);
+
+	serial_delay();
+	gpio_clear(PORT_MIXER, PIN_MIXER_SCLK);
+
+	serial_delay();
+	gpio_set(PORT_MIXER, PIN_MIXER_SCLK);
+
+	serial_delay();
+	gpio_clear(PORT_MIXER, PIN_MIXER_SCLK);
+
+	/* start transaction by bringing ENX low */
+	gpio_clear(PORT_MIXER, PIN_MIXER_ENX);
+
+	while (bits--) {
+		if (data & msb)
+			gpio_set(PORT_MIXER, PIN_MIXER_SDATA);
+		else
+			gpio_clear(PORT_MIXER, PIN_MIXER_SDATA);
+		data <<= 1;
+
+		serial_delay();
+		gpio_set(PORT_MIXER, PIN_MIXER_SCLK);
+
+		serial_delay();
+		gpio_clear(PORT_MIXER, PIN_MIXER_SCLK);
+	}
+
+	serial_delay();
+	gpio_set(PORT_MIXER, PIN_MIXER_ENX);
+#endif
+}
+
+uint16_t rffc5071_reg_read(uint8_t r)
+{
+	/* Readback register is not cached. */
+	if (r == RFFC5071_READBACK_REG)
+		return rffc5071_spi_read(r);
+
+	/* Discard uncommited write when reading. This shouldn't
+	 * happen, and probably has not been tested. */
+	if ((rffc5071_regs_dirty >> r) & 0x1) {
+		rffc5071_spi_read(r);
+	};
+	return rffc5071_regs[r];
+}
+
+void rffc5071_reg_write(uint8_t r, uint16_t v)
+{
+	rffc5071_regs[r] = v;
+	rffc5071_spi_write(r, v);
+	RFFC5071_REG_SET_CLEAN(r);
+}
+
+static inline void rffc5071_reg_commit(uint8_t r)
+{
+	rffc5071_reg_write(r,rffc5071_regs[r]);
+}
+
+void rffc5071_regs_commit(void)
+{
+	int r;
+	for(r = 0; r < RFFC5071_NUM_REGS; r++) {
+		if ((rffc5071_regs_dirty >> r) & 0x1) {
+			rffc5071_reg_commit(r);
+		}
+	}
+}
+
+void rffc5071_tx(void) {
+	LOG("# rffc5071_tx\n");
+	set_RFFC5071_ENBL(0);
+	set_RFFC5071_FULLD(0);
+	set_RFFC5071_MODE(0); /* mixer 1 only (TX) */
+	rffc5071_regs_commit();
+
+	rffc5071_enable();
+}
+
+void rffc5071_rx(void) {
+	LOG("# rfc5071_rx\n");
+	set_RFFC5071_ENBL(0);
+	set_RFFC5071_FULLD(0);
+	set_RFFC5071_MODE(1); /* mixer 2 only (RX) */
+	rffc5071_regs_commit();
+
+	rffc5071_enable();
+}
+
+void rffc5071_rxtx(void) {
+	LOG("# rfc5071_rxtx\n");
+	set_RFFC5071_ENBL(0);
+	set_RFFC5071_FULLD(1); /* mixer 1 and mixer 2 (RXTX) */
+	rffc5071_regs_commit();
+
+	rffc5071_enable();
+}
+
+void rffc5071_disable(void)  {
+	LOG("# rfc5071_disable\n");
+	set_RFFC5071_ENBL(0);
+	rffc5071_regs_commit();
+}
+
+void rffc5071_enable(void)  {
+	LOG("# rfc5071_enable\n");
+	set_RFFC5071_ENBL(1);
+	rffc5071_regs_commit();
+}
+
+#define LO_MAX 5400
+#define REF_FREQ 50
+
+/* configure frequency synthesizer in integer mode (lo in MHz) */
+uint16_t rffc5071_config_synth_int(uint16_t lo) {
+	uint8_t lodiv;
+	uint16_t fvco;
+	uint8_t fbkdiv;
+	uint16_t n;
+	uint16_t tune_freq;
+
+	LOG("# config_synth_int\n");
+
+	/* Calculate n_lo */
+	uint8_t n_lo = 0;
+	uint16_t x = LO_MAX / lo;
+	while (x > 1) {
+		n_lo++;
+		x >>= 1;
+	}
+
+	lodiv = 1 << n_lo;
+	fvco = lodiv * lo;
+
+	/* higher divider and charge pump current required above
+	 * 3.2GHz. Programming guide says these values (fbkdiv, n,
+	 * maybe pump?) can be changed back after enable in order to
+	 * improve phase noise, since the VCO will already be stable
+	 * and will be unaffected. */
+	if (fvco > 3200) {
+		fbkdiv = 4;
+		set_RFFC5071_PLLCPL(3);
+	} else {
+		fbkdiv = 2;
+		set_RFFC5071_PLLCPL(2);
+	}
+
+	n = (fvco / fbkdiv) / REF_FREQ;
+	tune_freq = 50*n*fbkdiv/lodiv;
+	LOG("# lo=%d n_lo=%d lodiv=%d fvco=%d fbkdiv=%d n=%d tune_freq=%d\n",
+	    lo, n_lo, lodiv, fvco, fbkdiv, n, tune_freq);
+
+	/* Path 1 */
+	set_RFFC5071_P1LODIV(lodiv);
+	set_RFFC5071_P1N(n);
+	set_RFFC5071_P1PRESC(fbkdiv >> 1);
+	set_RFFC5071_P1NMSB(0);
+	set_RFFC5071_P1NLSB(0);
+
+	/* Path 2 */
+	set_RFFC5071_P2LODIV(lodiv);
+	set_RFFC5071_P2N(n);
+	set_RFFC5071_P2PRESC(fbkdiv >> 1);
+	set_RFFC5071_P2NMSB(0);
+	set_RFFC5071_P2NLSB(0);
+
+	rffc5071_regs_commit();
+
+	return tune_freq;
+}
+
+/* !!!!!!!!!!! hz is currently ignored !!!!!!!!!!!
+ *
+ * Tuning is rounded down to the nearest 25MHz or 50MHz depending on
+ * frequency requsted. Actual tuned value in MHz is returned. */
+uint16_t rffc5071_set_frequency(uint16_t mhz, uint32_t hz) {
+	uint16_t tune_freq;
+
+	rffc5071_disable();
+	tune_freq = rffc5071_config_synth_int(mhz);
+	rffc5071_enable();
+
+	return tune_freq;
+}
+
+#ifdef TEST
+int main(int ac, char **av)
+{
+	rffc5071_setup();
+	rffc5071_tx();
+	rffc5071_set_frequency(500, 0);
+	rffc5071_set_frequency(525, 0);
+	rffc5071_set_frequency(550, 0);
+	rffc5071_set_frequency(1500, 0);
+	rffc5071_set_frequency(1525, 0);
+	rffc5071_set_frequency(1550, 0);
+	rffc5071_disable();
+	rffc5071_rx();
+	rffc5071_disable();
+	rffc5071_rxtx();
+	rffc5071_disable();
+}
+#endif //TEST
diff --git a/firmware/common/rffc5071.h b/firmware/common/rffc5071.h
index f9d25c56..c9a5e08e 100644
--- a/firmware/common/rffc5071.h
+++ b/firmware/common/rffc5071.h
@@ -19,45 +19,47 @@
  * Boston, MA 02110-1301, USA.
  */
 
-#include <stdint.h>
+#ifndef __RFFC5071_H
+#define __RFFC5071_H
 
-/* register names */
-#define RFFC5071_LF       0x00
-#define RFFC5071_XO       0x01
-#define RFFC5071_CAL_TIME 0x02
-#define RFFC5071_VCO_CTRL 0x03
-#define RFFC5071_CT_CAL1  0x04
-#define RFFC5071_CT_CAL2  0x05
-#define RFFC5071_PLL_CAL1 0x06
-#define RFFC5071_PLL_CAL2 0x07
-#define RFFC5071_VCO_AUTO 0x08
-#define RFFC5071_PLL_CTRL 0x09
-#define RFFC5071_PLL_BIAS 0x0A
-#define RFFC5071_MIX_CONT 0x0B
-#define RFFC5071_P1_FREQ1 0x0C
-#define RFFC5071_P1_FREQ2 0x0D
-#define RFFC5071_P1_FREQ3 0x0E
-#define RFFC5071_P2_FREQ1 0x0F
-#define RFFC5071_P2_FREQ2 0x10
-#define RFFC5071_P2_FREQ3 0x11
-#define RFFC5071_FN_CTRL  0x12
-#define RFFC5071_EXT_MOD  0x13
-#define RFFC5071_FMOD     0x14
-#define RFFC5071_SDI_CTRL 0x15
-#define RFFC5071_GPO      0x16
-#define RFFC5071_T_VCO    0x17
-#define RFFC5071_IQMOD1   0x18
-#define RFFC5071_IQMOD2   0x19
-#define RFFC5071_IQMOD3   0x1A
-#define RFFC5071_IQMOD4   0x1B
-#define RFFC5071_T_CTRL   0x1C
-#define RFFC5071_DEV_CTRL 0x1D
-#define RFFC5071_TEST     0x1E
-#define RFFC5071_READBACK 0x1F
+/* 31 registers, each containing 16 bits of data. */
+#define RFFC5071_NUM_REGS 31
 
-void rffc5071_init(void);
-void rffc5071_config_synth_int(uint16_t lo);
-void rffc5071_enable_tx(void);
-void rffc5071_enable_rx(void);
-void rffc5071_reg_write(uint8_t reg, uint16_t val);
-uint16_t rffc5071_reg_read(uint8_t reg);
+extern uint16_t rffc5071_regs[RFFC5071_NUM_REGS];
+extern uint32_t rffc5071_regs_dirty;
+
+#define RFFC5071_REG_SET_CLEAN(r) rffc5071_regs_dirty &= ~(1UL<<r)
+#define RFFC5071_REG_SET_DIRTY(r) rffc5071_regs_dirty |= (1UL<<r)
+
+/* Initialize chip. Call _setup() externally, as it calls _init(). */
+extern void rffc5071_init(void);
+extern void rffc5071_setup(void);
+
+/* Read a register via SPI. Save a copy to memory and return
+ * value. Discard any uncommited changes and mark CLEAN. */
+extern uint16_t rffc5071_reg_read(uint8_t r);
+
+/* Write value to register via SPI and save a copy to memory. Mark
+ * CLEAN. */
+extern void rffc5071_reg_write(uint8_t r, uint16_t v);
+
+/* Write all dirty registers via SPI from memory. Mark all clean. Some
+ * operations require registers to be written in a certain order. Use
+ * provided routines for those operations. */
+extern void rffc5071_regs_commit(void);
+
+/* Set frequency (MHz). The 'hz' field is currently ignored. Actual
+ * tune frequency (MHz) is returned. Expect requested freq to be
+ * rounded down to the nearest multiple of 25MHz or 50MHz, depending
+ * internal calculations. */
+extern uint16_t rffc5071_set_frequency(uint16_t mhz, uint32_t hz);
+
+/* Set up rx only, tx only, or full duplex. Chip should be disabled
+ * before _tx, _rx, or _rxtx are called. */
+extern void rffc5071_tx(void);
+extern void rffc5071_rx(void);
+extern void rffc5071_rxtx(void);
+extern void rffc5071_enable(void);
+extern void rffc5071_disable(void);
+
+#endif // __RFFC5071_H
diff --git a/firmware/common/rffc5071_regs.def b/firmware/common/rffc5071_regs.def
new file mode 100644
index 00000000..a40451fe
--- /dev/null
+++ b/firmware/common/rffc5071_regs.def
@@ -0,0 +1,257 @@
+/* -*- mode: c -*-
+ *
+ * Copyright 2012 Michael Ossmann
+ *
+ * This file is part of HackRF.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+#ifndef __RFFC5071_REGS_DEF
+#define __RFFC5071_REGS_DEF
+
+#define RFFC5071_READBACK_REG 31
+
+/* Generate static inline accessors that operate on the global
+ * regs. Done this way to (1) allow defs to be scraped out and used
+ * elsewhere, e.g. in scripts, (2) to avoid dealing with endian
+ * (structs). This may be used in firmware, or on host predefined
+ * register loads. */
+
+/* On set_, register is always set dirty, even if nothing
+ * changed. This makes sure that writes that have side effects,
+ * e.g. frequency setting, are not skipped. */
+
+/* n=name, r=regnum, o=offset (bits from LSB) of LSB of field,
+ * l=length (bits) */
+#define __MREG__(n,r,o,l) \
+static inline uint16_t get_##n(void) { \
+        return (rffc5071_regs[r] >> o) & ((1<<l)-1); \
+} \
+static inline void set_##n(uint16_t v) {      \
+	rffc5071_regs[r] &= ~(((1<<l)-1)<<o);  \
+	rffc5071_regs[r] |= ((v&((1<<l)-1))<<o); \
+	RFFC5071_REG_SET_DIRTY(r); \
+}
+
+/* REG 00 (0): LF */
+__MREG__(RFFC5071_PLLCPL,0,0,3)
+__MREG__(RFFC5071_P1CPDEF,0,3,6)
+__MREG__(RFFC5071_P2CPDEF,0,9,6)
+__MREG__(RFFC5071_IFACT,0,15,1)
+#define RFFC5071_
+
+/* REG 01 (1): XO */
+__MREG__(RFFC5071_SUWAIT,1,0,10)
+__MREG__(RFFC5071_XOCF,1,10,1)
+__MREG__(RFFC5071_XOC,1,11,4)
+__MREG__(RFFC5071_XOCH,1,15,1)
+
+/* REG 02 (2): CAL_TIME */
+__MREG__(RFFC5071_TKV2,2,0,4)
+__MREG__(RFFC5071_TKV1,2,4,4)
+__MREG__(RFFC5071_TCT,2,10,5)
+__MREG__(RFFC5071_WAIT,2,15,1)
+
+/* REG 03 (3): VCO_CTRL */
+__MREG__(RFFC5071_ICPUP,3,1,2)
+__MREG__(RFFC5071_REFST,3,3,1)
+__MREG__(RFFC5071_XOI3,3,4,1)
+__MREG__(RFFC5071_XOI2,3,5,1)
+__MREG__(RFFC5071_XOI1,3,6,1)
+__MREG__(RFFC5071_KVPOL,3,7,1)
+__MREG__(RFFC5071_KVRNG,3,8,1)
+__MREG__(RFFC5071_KVAVG,3,9,2)
+__MREG__(RFFC5071_CLKPL,3,1,1)
+__MREG__(RFFC5071_CTPOL,3,12,1)
+__MREG__(RFFC5071_CTAVG,3,13,2)
+__MREG__(RFFC5071_XTVCO,3,15,1)
+
+/* REG 04 (4): CT_CAL1 */
+__MREG__(RFFC5071_P1CTDEF,4,0,7)
+__MREG__(RFFC5071_P1CT,4,7,1)
+__MREG__(RFFC5071_P1CTV,4,8,5)
+__MREG__(RFFC5071_P1CTGAIN,4,13,3)
+
+/* REG 05 (5): CT_CAL2 */
+__MREG__(RFFC5071_P2CTDEF,5,0,7)
+__MREG__(RFFC5071_P2CT,5,7,1)
+__MREG__(RFFC5071_P2CTV,5,8,5)
+__MREG__(RFFC5071_P2CTGAIN,5,13,3)
+
+/* REG 06 (6): PLL_CAL1 */
+__MREG__(RFFC5071_P1SGN,6,2,1)
+__MREG__(RFFC5071_P1KVGAIN,6,3,3)
+__MREG__(RFFC5071_P1DN,6,6,9)
+__MREG__(RFFC5071_P1KV,6,15,1)
+
+/* REG 07 (7): PLL_CAL2 */
+__MREG__(RFFC5071_P2SGN,7,2,1)
+__MREG__(RFFC5071_P2KVGAIN,7,3,3)
+__MREG__(RFFC5071_P2DB,7,6,9)
+__MREG__(RFFC5071_P2KV,7,15,1)
+
+/* REG 08 (8): VCO_AUTO */
+__MREG__(RFFC5071_CTMIN,8,1,7)
+__MREG__(RFFC5071_CTMAX,8,8,7)
+__MREG__(RFFC5071_AUTO,8,15,1)
+
+/* REG 09 (9): PLL_CTRL */
+__MREG__(RFFC5071_PLLDY,9,0,2)
+__MREG__(RFFC5071_ALOI,9,2,1)
+__MREG__(RFFC5071_RELOK,9,3,1)
+__MREG__(RFFC5071_LDLEV,9,4,1)
+__MREG__(RFFC5071_LDEN,9,5,1)
+__MREG__(RFFC5071_TVCO,9,6,5)
+__MREG__(RFFC5071_PLLST,9,11,1)
+__MREG__(RFFC5071_CLKDIV,9,12,3)
+__MREG__(RFFC5071_DIVBY,9,15,1)
+
+/* REG 0A (10): PLL_BIAS */
+__MREG__(RFFC5071_P2VCOI,10,0,3)
+__MREG__(RFFC5071_P2LOI,10,3,4)
+__MREG__(RFFC5071_P1VCOI,10,8,3)
+__MREG__(RFFC5071_P1LOI,10,11,4)
+
+/* REG 0B (11): MIX_CONT */
+__MREG__(RFFC5071_P2MIXIDD,11,9,3)
+__MREG__(RFFC5071_P1MIXIDD,11,12,3)
+__MREG__(RFFC5071_FULLD,11,15,1)
+
+/* REG 0C (12): P1_FREQ1 */
+__MREG__(RFFC5071_P1VCOSEL,12,0,2)
+__MREG__(RFFC5071_P1PRESC,12,2,2)
+__MREG__(RFFC5071_P1LODIV,12,4,3)
+__MREG__(RFFC5071_P1N,12,7,9)
+
+/* REG 0D (13): P1_FREQ2 */ /* !!!!! CHECK FOR OVERFLOW !!!!! */
+__MREG__(RFFC5071_P1NMSB,13,0,16)
+
+/* REG 0E (14): P1_FREQ3 */
+__MREG__(RFFC5071_P1NLSB,14,8,8)
+
+/* REG 0F (15): P2_FREQ1 */
+__MREG__(RFFC5071_P2VCOSEL,15,0,2)
+__MREG__(RFFC5071_P2PRESC,15,2,2)
+__MREG__(RFFC5071_P2LODIV,15,4,3)
+__MREG__(RFFC5071_P2N,15,7,9)
+
+/* REG 10 (16): P2_FREQ2 */ /* !!!!! CHECK FOR OVERFLOW !!!!! */
+__MREG__(RFFC5071_P2NMSB,16,0,16)
+
+/* REG 11 (17): P2_FREQ3 */
+__MREG__(RFFC5071_P2NLSB,17,8,8)
+
+/* REG 12 (18): FN_CTRL */
+__MREG__(RFFC5071_TZPS,18,1,1)
+__MREG__(RFFC5071_DMODE,18,2,1)
+__MREG__(RFFC5071_FM,18,3,1)
+__MREG__(RFFC5071_DITH,18,4,1)
+__MREG__(RFFC5071_DSM_MODE,18,5,1)
+__MREG__(RFFC5071_PHSALNDLY,18,6,2)
+__MREG__(RFFC5071_PHSALNGAIN,18,8,3)
+__MREG__(RFFC5071_PHALN,18,11,1)
+__MREG__(RFFC5071_SDM,18,12,2)
+__MREG__(RFFC5071_DITHR,18,14,1)
+__MREG__(RFFC5071_FNZ,18,15,1)
+
+/* REG 13 (19): EXT_MOD */
+__MREG__(RFFC5071_MODSTEP,19,10,4)
+__MREG__(RFFC5071_MODSETUP,19,14,2)
+
+/* REG 14 (20): FMOD */ /* !!!!! CHECK FOR OVERFLOW !!!!! */
+__MREG__(RFFC5071_MODULATION,20,0,16)
+
+/* REG 15 (21): SDI_CTRL */
+__MREG__(RFFC5071_RESET,21,1,1)
+__MREG__(RFFC5071_ADDR,21,11,1)
+__MREG__(RFFC5071_4WIRE,21,12,1)
+__MREG__(RFFC5071_MODE,21,13,1)
+__MREG__(RFFC5071_ENBL,21,14,1)
+__MREG__(RFFC5071_SIPIN,21,15,1)
+
+/* REG 16 (22): GPO */
+__MREG__(RFFC5071_LOCK,22,0,1)
+__MREG__(RFFC5071_GATE,22,1,1)
+__MREG__(RFFC5071_P1GPO,22,2,7)
+__MREG__(RFFC5071_P2GPO,22,9,7)
+
+/* REG 17 (23): T_VCO */
+__MREG__(RFFC5071_CURVE_VCO3,23,7,3)
+__MREG__(RFFC5071_CURVE_VCO2,23,10,3)
+__MREG__(RFFC5071_CURVE_VCO1,23,13,3)
+
+/* REG 18 (24): IQMOD1 */
+__MREG__(RFFC5071_BUFDC,24,0,2)
+__MREG__(RFFC5071_DIVBIAS,24,2,1)
+__MREG__(RFFC5071_CALBLK,24,3,1)
+__MREG__(RFFC5071_CALNUL,24,4,1)
+__MREG__(RFFC5071_CALON,24,5,1)
+__MREG__(RFFC5071_LOBIAS,24,6,2)
+__MREG__(RFFC5071_MODBIAS,24,8,3)
+__MREG__(RFFC5071_CTRL,24,11,5)   /* shown as 5 fields in reg overview */
+
+/* REG 19 (25): IQMOD2 */
+__MREG__(RFFC5071_MODBUF,25,0,2)
+__MREG__(RFFC5071_MOD,25,2,2)
+__MREG__(RFFC5071_CALATTEN,25,4,2)
+__MREG__(RFFC5071_RCTUNE,25,6,6)
+__MREG__(RFFC5071_BBATTEN,25,12,4)
+
+/* REG 1A (26): IQMOD3 */
+__MREG__(RFFC5071_DACEN,26,3,1)
+__MREG__(RFFC5071_BUFDACQ,26,4,6)
+__MREG__(RFFC5071_BUFDACI,26,10,6)
+
+/* REG 1B (27): IQMOD4 */
+__MREG__(RFFC5071_BUFBIAS2,27,2,2)
+__MREG__(RFFC5071_BUFBIAS1,27,4,2)
+__MREG__(RFFC5071_MODDACQ,27,6,6)
+__MREG__(RFFC5071_MODDACI,27,12,6)
+
+/* REG 1C (28): T_CTRL */
+__MREG__(RFFC5071_V_TEST,28,5,1)
+__MREG__(RFFC5071_LDO_BY,28,6,1)
+__MREG__(RFFC5071_EXT_FILT,28,7,1)
+__MREG__(RFFC5071_REF_SEL,28,8,1)
+__MREG__(RFFC5071_FILT_CTRL,28,9,2)
+__MREG__(RFFC5071_FC_EN,28,11,1)
+__MREG__(RFFC5071_TBL_SEL,28,12,2)
+__MREG__(RFFC5071_TC_EN,28,14,2)
+
+/* REG 1D (29): DEV_CTRL */
+__MREG__(RFFC5071_BYPAS,29,1,1)
+__MREG__(RFFC5071_CTCLK,29,2,1)
+__MREG__(RFFC5071_DAC,29,3,1)
+__MREG__(RFFC5071_CPD,29,4,1)
+__MREG__(RFFC5071_CPU,29,5,1)
+__MREG__(RFFC5071_RSMSTOPST,29,6,5)
+__MREG__(RFFC5071_RSMST,29,11,1)
+__MREG__(RFFC5071_READSEL,29,12,4)
+
+/* REG 1E (30): TEST */
+__MREG__(RFFC5071_LFSRD,30,0,1)     /* n/a in reg overview */
+__MREG__(RFFC5071_RCBYP,30,1,1)
+__MREG__(RFFC5071_RGBYP,30,2,1)
+__MREG__(RFFC5071_LFSRT,30,3,1)
+__MREG__(RFFC5071_LFSRGATET,30,4,4)
+__MREG__(RFFC5071_LFSRP,30,8,1)
+__MREG__(RFFC5071_LFSR,30,9,1)
+__MREG__(RFFC5071_TSEL,30,10,2)
+__MREG__(RFFC5071_TMUX,30,12,3)
+__MREG__(RFFC5071_TEN,30,15,1)
+
+#endif // __RFFC5071_REGS_DEF
diff --git a/firmware/mixertx/mixertx.c b/firmware/mixertx/mixertx.c
index ea41bb21..600e7d6b 100644
--- a/firmware/mixertx/mixertx.c
+++ b/firmware/mixertx/mixertx.c
@@ -61,14 +61,13 @@ int main(void)
 	pin_setup();
 	gpio_set(PORT_EN1V8, PIN_EN1V8); /* 1V8 on */
 	cpu_clock_init();
-    ssp1_init();
+	ssp1_init();
 
 	gpio_set(PORT_LED1_3, (PIN_LED1)); /* LED1 on */
 
 	ssp1_set_mode_max2837();
 	max2837_setup();
-	rffc5071_init();
-	rffc5071_reg_write(RFFC5071_GPO, 0x0001); /* PLL lock output on GPO4 */
+	rffc5071_setup();
 	gpio_set(PORT_LED1_3, (PIN_LED2)); /* LED2 on */
 
 	max2837_set_frequency(freq);
diff --git a/firmware/sgpio-rx/sgpio-rx.c b/firmware/sgpio-rx/sgpio-rx.c
index aefd86e6..afb168a0 100644
--- a/firmware/sgpio-rx/sgpio-rx.c
+++ b/firmware/sgpio-rx/sgpio-rx.c
@@ -325,10 +325,11 @@ int main(void) {
     ssp1_init();
 	ssp1_set_mode_max2837();
 	max2837_setup();
-	rffc5071_init();
-	rffc5071_config_synth_int(500);
-	rffc5071_enable_rx();
-	//rffc5071_reg_write(RFFC5071_GPO, 0x0001); /* PLL lock output on GPO4 */
+	rffc5071_setup();
+	rffc5071_rx();
+	rffc5071_set_frequency(500, 0); // 500 MHz, 0 Hz (Hz ignored)
+
+#ifdef LOLLIPOP_SWITCH_SET_UP_DONE_IN_RFFC5071
 	/* lollipop */
 	uint8_t gpo = 
 			  (1 << 0)  /* SWTXB1 (!tx_bypass) */
@@ -347,6 +348,7 @@ int main(void) {
 			//| (0 << 5); /* !AMP_PWR */
 	rffc5071_reg_write(RFFC5071_GPO, (gpo << 9) | (gpo << 2) | 0x3);
 	gpio_set(PORT_LED1_3, (PIN_LED1)); /* LED1 on */
+#endif
 
 	max2837_set_frequency(freq);
 	max2837_start();