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Cleanup on xxx_rom_to_ram directory now it contains only makefile, removed redundant .c file from xxx dir.

Browse Source 
Fixed IAP "IAP_CMD_READ_SERIAL_NO" for LPC43xx flashless part not supporting IAP by using SPIFI w25q80bv Unique ID(64bits).
Fixed SPIFI erase/program also now it with check SPIFI w25q80bv Device ID = 0x13 at start of w25q80bv_setup()/w25q80bv_chip_erase()/w25q80bv_program().
This commit is contained in:
TitanMKD
2013-04-07 18:55:12 +02:00
parent c5a799c134
commit 8777f93721
12 changed files with 207 additions and 2573 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
firmware/Makefile
View File

@ -21,6 +21,7 @@
#
TARGETS = blinky \
blinky_rom_to_ram \
mixertx \
sgpio \
sgpio-rx \
@ -28,7 +29,8 @@ TARGETS = blinky \
startup \
startup_systick \
startup_systick_perfo \
usb_performance
usb_performance \
usb_performance_rom_to_ram
# blinky_rom_to_ram
# sgpio_passthrough_rom_to_ram

14
firmware/blinky_rom_to_ram/Makefile
View File

@ -1,7 +1,6 @@
# Hey Emacs, this is a -*- makefile -*-
#
# Copyright 2012 Michael Ossmann <mike@ossmann.com>
# Copyright 2012 Jared Boone <jared@sharebrained.com>
# Copyright 2013 Benjamin Vernoux <titanmkd@gmail.com>
#
# This file is part of HackRF.
#
@ -21,12 +20,19 @@
# Boston, MA 02110-1301, USA.
#
BINARY = blinky
BINARY = blinky_rom_to_ram
SRC = $(BINARY).c \
SRC_DIR = blinky
SRC = blinky.c \
../common/hackrf_core.c \
../common/si5351c.c \
../common/max2837.c
LDSCRIPT = ../common/LPC4330_M4_rom_to_ram.ld
%.o: ../$(SRC_DIR)/%.c Makefile
@printf " CC $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(CC) $(CFLAGS) -o $@ -c $<
include ../common/Makefile_inc.mk

54
firmware/blinky_rom_to_ram/blinky.c
View File

@ -1,54 +0,0 @@
/*
* Copyright 2010 - 2012 Michael Ossmann
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#include <libopencm3/lpc43xx/gpio.h>
#include <libopencm3/lpc43xx/scu.h>
#include "hackrf_core.h"
u32 boot0, boot1, boot2, boot3;
int main(void)
{
int i;
pin_setup();
/* Set 1V8 */
gpio_set(PORT_EN1V8, PIN_EN1V8);
/* Blink LED1/2/3 on the board and Read BOOT0/1/2/3 pins. */
while (1)
{
boot0 = BOOT0_STATE;
boot1 = BOOT1_STATE;
boot2 = BOOT2_STATE;
boot3 = BOOT3_STATE;
gpio_set(PORT_LED1_3, (PIN_LED1|PIN_LED2|PIN_LED3)); /* LEDs on */
for (i = 0; i < 2000000; i++) /* Wait a bit. */
__asm__("nop");
gpio_clear(PORT_LED1_3, (PIN_LED1|PIN_LED2|PIN_LED3)); /* LED off */
for (i = 0; i < 2000000; i++) /* Wait a bit. */
__asm__("nop");
}
return 0;
}

18
firmware/common/rom_iap.c
View File

@ -23,12 +23,12 @@
#include <stdint.h>
#include "rom_iap.h"
#include "w25q80bv.h"
#define ROM_IAP_ADDR (0x10400100)
#define ROM_IAP_UNDEF_ADDR (0x12345678)
#define ROM_OTP_PART_ID_ADDR (0x40045000)
#define ROM_OTP_SERIAL_NO_ADDR (0x40045050) /* To be confirmed */
typedef void (* IAP_t)(uint32_t [],uint32_t[]);
@ -73,7 +73,12 @@ isp_iap_ret_code_t iap_cmd_call(iap_cmd_res_t* iap_cmd_res)
pROM_API->IAP( (uint32_t*)&iap_cmd_res->cmd_param, (uint32_t*)&iap_cmd_res->status_res);
}else
{
/* Alternative way to retrieve Part Id & Serial No on MCU with no IAP */
/*
Alternative way to retrieve Part Id on MCU with no IAP
Read Serial No => Read Unique ID in SPIFI (only compatible with W25Q80BV
*/
w25q80bv_setup();
switch(iap_cmd_res->cmd_param.command_code)
{
case IAP_CMD_READ_PART_ID_NO:
@ -84,11 +89,10 @@ isp_iap_ret_code_t iap_cmd_call(iap_cmd_res_t* iap_cmd_res)
break;
case IAP_CMD_READ_SERIAL_NO:
p_u32_data = (uint32_t*)ROM_OTP_SERIAL_NO_ADDR;
iap_cmd_res->status_res.iap_result[0] = p_u32_data[0];
iap_cmd_res->status_res.iap_result[1] = p_u32_data[1];
iap_cmd_res->status_res.iap_result[2] = p_u32_data[2];
iap_cmd_res->status_res.iap_result[3] = p_u32_data[3];
/* Only 64bits used */
iap_cmd_res->status_res.iap_result[0] = 0;
iap_cmd_res->status_res.iap_result[1] = 0;
w25q80bv_get_unique_id( (w25q80bv_unique_id_t*)&iap_cmd_res->status_res.iap_result[2] );
iap_cmd_res->status_res.status_ret = CMD_SUCCESS;
break;

77
firmware/common/w25q80bv.c
View File

@ -1,5 +1,6 @@
/*
* Copyright 2013 Michael Ossmann
* Copyright 2013 Benjamin Vernoux
*
* This file is part of HackRF.
*
@ -31,6 +32,7 @@
#include <libopencm3/lpc43xx/ssp.h>
#include <libopencm3/lpc43xx/scu.h>
#include <libopencm3/lpc43xx/gpio.h>
#include <libopencm3/lpc43xx/rgu.h>
/*
* Set up pins for GPIO and SPI control, configure SSP0 peripheral for SPI.
@ -39,9 +41,21 @@
void w25q80bv_setup(void)
{
uint8_t device_id;
const uint8_t serial_clock_rate = 2;
const uint8_t clock_prescale_rate = 2;
/* Reset SPIFI peripheral before to Erase/Write SPIFI memory through SPI */
RESET_CTRL1 = RESET_CTRL1_SPIFI_RST;
/* Init SPIFI GPIO to Normal GPIO */
scu_pinmux(P3_3, (SCU_SSP_IO | SCU_CONF_FUNCTION2)); // P3_3 SPIFI_SCK => SSP0_SCK
scu_pinmux(P3_4, (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)); // P3_4 SPIFI SPIFI_SIO3 IO3 => GPIO1[14]
scu_pinmux(P3_5, (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)); // P3_5 SPIFI SPIFI_SIO2 IO2 => GPIO1[15]
scu_pinmux(P3_6, (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)); // P3_6 SPIFI SPIFI_MISO IO1 => GPIO0[6]
scu_pinmux(P3_7, (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)); // P3_7 SPIFI SPIFI_MOSI IO0 => GPIO5[10]
scu_pinmux(P3_8, (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)); // P3_8 SPIFI SPIFI_CS => GPIO5[11]
/* configure SSP pins */
scu_pinmux(SCU_SSP0_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(SCU_SSP0_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
@ -70,6 +84,12 @@ void w25q80bv_setup(void)
SSP_MODE_NORMAL,
SSP_MASTER,
SSP_SLAVE_OUT_ENABLE);
device_id = 0;
while(device_id != W25Q80BV_DEVICE_ID_RES)
{
device_id = w25q80bv_get_device_id();
}
}
uint8_t w25q80bv_get_status(void)
@ -84,6 +104,48 @@ uint8_t w25q80bv_get_status(void)
return value;
}
/* Release power down / Device ID */
uint8_t w25q80bv_get_device_id(void)
{
uint8_t value;
gpio_clear(PORT_SSP0_SSEL, PIN_SSP0_SSEL);
ssp_transfer(SSP0_NUM, W25Q80BV_DEVICE_ID);
/* Read 3 dummy bytes */
value = ssp_transfer(SSP0_NUM, 0xFF);
value = ssp_transfer(SSP0_NUM, 0xFF);
value = ssp_transfer(SSP0_NUM, 0xFF);
/* Read Device ID shall return 0x13 for W25Q80BV */
value = ssp_transfer(SSP0_NUM, 0xFF);
gpio_set(PORT_SSP0_SSEL, PIN_SSP0_SSEL);
return value;
}
void w25q80bv_get_unique_id(w25q80bv_unique_id_t* unique_id)
{
int i;
uint8_t value;
gpio_clear(PORT_SSP0_SSEL, PIN_SSP0_SSEL);
ssp_transfer(SSP0_NUM, W25Q80BV_UNIQUE_ID);
/* Read 4 dummy bytes */
for(i=0; i<4; i++)
value = ssp_transfer(SSP0_NUM, 0xFF);
/* Read Unique ID 64bits (8*8) */
for(i=0; i<8; i++)
{
value = ssp_transfer(SSP0_NUM, 0xFF);
unique_id->id_8b[i] = value;
}
gpio_set(PORT_SSP0_SSEL, PIN_SSP0_SSEL);
}
void w25q80bv_wait_while_busy(void)
{
while (w25q80bv_get_status() & W25Q80BV_STATUS_BUSY);
@ -99,6 +161,14 @@ void w25q80bv_write_enable(void)
void w25q80bv_chip_erase(void)
{
uint8_t device_id;
device_id = 0;
while(device_id != W25Q80BV_DEVICE_ID_RES)
{
device_id = w25q80bv_get_device_id();
}
w25q80bv_write_enable();
w25q80bv_wait_while_busy();
gpio_clear(PORT_SSP0_SSEL, PIN_SSP0_SSEL);
@ -136,6 +206,13 @@ void w25q80bv_page_program(const uint32_t addr, const uint16_t len, const uint8_
void w25q80bv_program(uint32_t addr, uint32_t len, const uint8_t* data)
{
uint16_t first_block_len;
uint8_t device_id;
device_id = 0;
while(device_id != W25Q80BV_DEVICE_ID_RES)
{
device_id = w25q80bv_get_device_id();
}
/* do nothing if we would overflow the flash */
if ((len > W25Q80BV_NUM_BYTES) || (addr > W25Q80BV_NUM_BYTES)

15
firmware/common/w25q80bv.h
View File

@ -1,5 +1,6 @@
/*
* Copyright 2013 Michael Ossmann
* Copyright 2013 Benjamin Vernoux
*
* This file is part of HackRF.
*
@ -30,11 +31,25 @@
#define W25Q80BV_CHIP_ERASE 0xC7
#define W25Q80BV_READ_STATUS1 0x05
#define W25Q80BV_PAGE_PROGRAM 0x02
#define W25Q80BV_DEVICE_ID 0xAB
#define W25Q80BV_UNIQUE_ID 0x4B
#define W25Q80BV_STATUS_BUSY 0x01
#define W25Q80BV_DEVICE_ID_RES 0x13 /* Expected device_id for W25Q80BV */
typedef union
{
uint64_t id_64b;
uint32_t id_32b[2]; /* 2*32bits 64bits Unique ID */
uint8_t id_8b[8]; /* 8*8bits 64bits Unique ID */
} w25q80bv_unique_id_t;
void w25q80bv_setup(void);
void w25q80bv_chip_erase(void);
void w25q80bv_program(uint32_t addr, uint32_t len, const uint8_t* data);
uint8_t w25q80bv_get_device_id(void);
void w25q80bv_get_unique_id(w25q80bv_unique_id_t* unique_id);
#endif//__W25Q80BV_H__

12
firmware/cpldjtagprog_rom_to_ram/Makefile
View File

@ -1,7 +1,6 @@
# Hey Emacs, this is a -*- makefile -*-
#
# Copyright 2012 Michael Ossmann <mike@ossmann.com>
# Copyright 2012 Jared Boone <jared@sharebrained.com>
# Copyright 2013 Benjamin Vernoux <titanmkd@gmail.com>
#
# This file is part of HackRF.
#
@ -23,7 +22,9 @@
BINARY = cpldjtagprog_rom_to_ram
SRC = $(BINARY).c \
SRC_DIR = cpldjtagprog
SRC = cpldjtagprog.c \
../common/hackrf_core.c \
../common/si5351c.c \
../common/max2837.c \
@ -33,4 +34,9 @@ SRC = $(BINARY).c \
../common/xapp058/ports.c
LDSCRIPT = ../common/LPC4330_M4_rom_to_ram.ld
%.o: ../$(SRC_DIR)/%.c Makefile
@printf " CC $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(CC) $(CFLAGS) -o $@ -c $<
include ../common/Makefile_inc.mk

72
firmware/cpldjtagprog_rom_to_ram/cpldjtagprog_rom_to_ram.c
View File

@ -1,72 +0,0 @@
/*
* Copyright 2010 - 2013 Michael Ossmann
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#include <libopencm3/lpc43xx/gpio.h>
#include <libopencm3/lpc43xx/scu.h>
#include "hackrf_core.h"
#include "cpld_jtag.h"
#include "../cpldjtagprog/sgpio_if_xsvf.h"
#define WAIT_LOOP_DELAY (6000000)
#define ALL_LEDS (PIN_LED1|PIN_LED2|PIN_LED3)
int main(void)
{
int i;
int error;
int LED;
pin_setup();
/* Set 1V8 */
gpio_set(PORT_EN1V8, PIN_EN1V8);
cpu_clock_init();
/* program test bitstream to CPLD */
error = cpld_jtag_program(sgpio_if_xsvf_len, &sgpio_if_xsvf[0]);
if(error == 0)
{
/* blink only LED1 (Green) on success */
LED = PIN_LED1;
}else
{
/* blink LED3 (Red) on error */
LED = PIN_LED3;
}
gpio_clear(PORT_LED1_3, ALL_LEDS); /* All LEDs off */
while (1)
{
gpio_set(PORT_LED1_3, LED); /* LEDs on */
for (i = 0; i < WAIT_LOOP_DELAY; i++) /* Wait a bit. */
__asm__("nop");
gpio_clear(PORT_LED1_3, LED); /* LED off */
for (i = 0; i < WAIT_LOOP_DELAY; i++) /* Wait a bit. */
__asm__("nop");
}
return 0;
}

28
firmware/startup_systick_perfo_rom_to_ram/Makefile
View File

@ -1,12 +1,38 @@
# Hey Emacs, this is a -*- makefile -*-
#
# Copyright 2013 Benjamin Vernoux <titanmkd@gmail.com>
#
# This file is part of HackRF.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
#
BINARY = startup_systick_perfo_rom_to_ram
SRC_DIR = startup_systick_perfo
SRC = startup_systick.c \
perf_mips.c \
../common/hackrf_core.c \
../common/si5351c.c \
../common/max2837.c
LDSCRIPT = ../common/LPC4330_M4_rom_to_ram.ld
%.o: ../$(SRC_DIR)/%.c Makefile
@printf " CC $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(CC) $(CFLAGS) -o $@ -c $<
include ../common/Makefile_inc.mk

2220
firmware/startup_systick_perfo_rom_to_ram/perf_mips.c
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File diff suppressed because it is too large Load Diff

209
firmware/startup_systick_perfo_rom_to_ram/startup_systick.c
View File

@ -1,209 +0,0 @@
/*
* Copyright 2010 - 2012 Michael Ossmann
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#include <libopencm3/lpc43xx/gpio.h>
#include <libopencm3/lpc43xx/scu.h>
#include <libopencm3/lpc43xx/i2c.h>
#include <libopencm3/lpc43xx/nvic.h>
#include <libopencm3/lpc43xx/systick.h>
#include <libopencm3/cm3/scs.h>
#include "hackrf_core.h"
/* Global counter incremented by SysTick Interrupt each millisecond */
volatile u32 g_ulSysTickCount;
u32 g_NbCyclePerSecond;
void systick_setup(void)
{
u32 systick_reload_val;
g_ulSysTickCount = 0;
/* Disable IRQ globally */
__asm__("cpsid i");
/* Set processor Clock as Source Clock */
systick_set_clocksource(STK_CTRL_CLKSOURCE);
/* Get SysTick calibration value to obtain by default 1 tick = 10ms */
systick_reload_val = systick_get_calib();
/*
* Calibration seems wrong on LPC43xx(TBC) for default Freq it assume System Clock is 12MHz but it is 12*17=204MHz
* Fix the Calibration value bu multiplication by 17
*/
systick_reload_val = (systick_reload_val*17);
/* To obtain 1ms per tick just divide by 10 the 10ms base tick and set the reload */
systick_reload_val = systick_reload_val/10;
systick_set_reload(systick_reload_val);
systick_interrupt_enable();
/* Start counting. */
systick_counter_enable();
/* Set SysTick Priority to maximum */
nvic_set_priority(NVIC_SYSTICK_IRQ, 0xFF);
/* Enable IRQ globally */
__asm__("cpsie i");
}
void scs_dwt_cycle_counter_enabled(void)
{
SCS_DEMCR |= SCS_DEMCR_TRCENA;
SCS_DWT_CTRL |= SCS_DWT_CTRL_CYCCNTENA;
}
u32 sys_tick_get_time_ms(void)
{
return g_ulSysTickCount;
}
u32 sys_tick_delta_time_ms(u32 start, u32 end)
{
#define MAX_T_U32 ((2^32)-1)
u32 diff;
if(end > start)
{
diff=end-start;
}else
{
diff=MAX_T_U32-(start-end)+1;
}
return diff;
}
void sys_tick_wait_time_ms(u32 wait_ms)
{
u32 start, end;
u32 tickms;
start = sys_tick_get_time_ms();
do
{
end = sys_tick_get_time_ms();
tickms = sys_tick_delta_time_ms(start, end);
}while(tickms < wait_ms);
}
/* Called each 1ms/1000Hz by interrupt
1) Count the number of cycle per second.
2) Increment g_ulSysTickCount counter.
*/
void sys_tick_handler(void)
{
if(g_ulSysTickCount==0)
{
/* Clear Cycle Counter*/
SCS_DWT_CYCCNT = 0;
}else if(g_ulSysTickCount==1000)
{
/* Capture number of cycle elapsed during 1 second */
g_NbCyclePerSecond = SCS_DWT_CYCCNT;
}
g_ulSysTickCount++;
}
u32 nb_inst_per_sec[16];
extern u32 test_nb_instruction_per_sec_100_nop_asm();
extern u32 test_nb_instruction_per_sec_105_nop_asm();
extern u32 test_nb_instruction_per_sec_110_nop_asm();
extern u32 test_nb_instruction_per_sec_115_nop_asm();
extern u32 test_nb_instruction_per_sec_120_nop_asm();
extern u32 test_nb_instruction_per_sec_150_nop_asm();
extern u32 test_nb_instruction_per_sec_200_nop_asm();
extern u32 test_nb_instruction_per_sec_1000_nop_asm();
#define LED1_TOGGLE() (gpio_toggle(PORT_LED1_3, (PIN_LED1)))
int main(void)
{
pin_setup();
gpio_set(PORT_EN1V8, PIN_EN1V8); /* 1V8 on */
cpu_clock_init();
scs_dwt_cycle_counter_enabled();
systick_setup();
gpio_clear(PORT_LED1_3, (PIN_LED1)); /* LED1 off */
/* Test number of instruction per second (MIPS) slow blink ON 1s, OFF 1s */
LED1_TOGGLE();
nb_inst_per_sec[0] = test_nb_instruction_per_sec_100_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[1]= test_nb_instruction_per_sec_105_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[2]= test_nb_instruction_per_sec_110_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[3]= test_nb_instruction_per_sec_115_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[4] = test_nb_instruction_per_sec_120_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[5] = test_nb_instruction_per_sec_150_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[6] = test_nb_instruction_per_sec_200_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[7] = test_nb_instruction_per_sec_1000_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[8] = test_nb_instruction_per_sec_100_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[9]= test_nb_instruction_per_sec_105_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[10]= test_nb_instruction_per_sec_110_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[11]= test_nb_instruction_per_sec_115_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[12] = test_nb_instruction_per_sec_120_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[13] = test_nb_instruction_per_sec_150_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[14] = test_nb_instruction_per_sec_200_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[15] = test_nb_instruction_per_sec_1000_nop_asm();
LED1_TOGGLE();
/* Test finished fast blink */
while (1)
{
gpio_set(PORT_LED1_3, (PIN_LED1)); /* LED1 on */
gpio_set(PORT_LED1_3, (PIN_LED2)); /* LED2 on */
gpio_set(PORT_LED1_3, (PIN_LED3)); /* LED3 on */
sys_tick_wait_time_ms(250);
gpio_clear(PORT_LED1_3, (PIN_LED3)); /* LED3 off */
gpio_clear(PORT_LED1_3, (PIN_LED2)); /* LED2 off */
gpio_clear(PORT_LED1_3, (PIN_LED1)); /* LED1 off */
sys_tick_wait_time_ms(250);
}
return 0;
}

53
firmware/usb_performance_rom_to_ram/Makefile Normal file
View File

@ -0,0 +1,53 @@
# Hey Emacs, this is a -*- makefile -*-
#
# Copyright 2013 Benjamin Vernoux <titanmkd@gmail.com>
#
# This file is part of HackRF.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
#
BINARY = usb_performance_rom_to_ram
SRC_DIR = usb_performance
SRC = usb_performance.c \
usb.c \
usb_request.c \
usb_standard_request.c \
usb_descriptor.c \
../common/fault_handler.c \
../common/hackrf_core.c \
../common/sgpio.c \
../common/si5351c.c \
../common/max2837.c \
../common/max5864.c \
../common/rffc5071.c \
../common/w25q80bv.c \
../common/cpld_jtag.c \
../common/xapp058/lenval.c \
../common/xapp058/micro.c \
../common/xapp058/ports.c \
../common/rom_iap.c
LDSCRIPT = ../common/LPC4330_M4_rom_to_ram.ld
%.o: ../$(SRC_DIR)/%.c Makefile
@printf " CC $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(CC) $(CFLAGS) -o $@ -c $<
include ../common/Makefile_inc.mk