si clock for the lpc
This commit is contained in:
Hoernchen
@ -90,23 +90,27 @@ bool sample_rate_set(const uint32_t sample_rate_hz) {
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switch(sample_rate_hz) {
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case 5000000:
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p1 = 9728; // 800MHz / 80 = 10 MHz (SGPIO), 5 MHz (codec)
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p1 = SI_INTDIV(80); // 800MHz / 80 = 10 MHz (SGPIO), 5 MHz (codec)
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break;
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case 8000000:
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p1 = SI_INTDIV(50); // 800MHz / 50 = 16 MHz (SGPIO), 8 MHz (codec)
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break;
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case 10000000:
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p1 = 4608; // 800MHz / 40 = 20 MHz (SGPIO), 10 MHz (codec)
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p1 = SI_INTDIV(40); // 800MHz / 40 = 20 MHz (SGPIO), 10 MHz (codec)
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break;
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case 12500000:
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p1 = 3584; // 800MHz / 32 = 25 MHz (SGPIO), 12.5 MHz (codec)
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p1 = SI_INTDIV(32); // 800MHz / 32 = 25 MHz (SGPIO), 12.5 MHz (codec)
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break;
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case 16000000:
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p1 = 2688; // 800MHz / 25 = 32 MHz (SGPIO), 16 MHz (codec)
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p1 = SI_INTDIV(25); // 800MHz / 25 = 32 MHz (SGPIO), 16 MHz (codec)
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break;
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case 20000000:
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p1 = 2048; // 800MHz / 20 = 40 MHz (SGPIO), 20 MHz (codec)
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p1 = SI_INTDIV(20); // 800MHz / 20 = 40 MHz (SGPIO), 20 MHz (codec)
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break;
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default:
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@ -117,13 +121,13 @@ bool sample_rate_set(const uint32_t sample_rate_hz) {
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si5351c_configure_multisynth(0, p1, 0, 1, 1);
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/* MS0/CLK1 is the source for the CPLD (CODEC_X2_CLK). */
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si5351c_configure_multisynth(1, p1, 0, 1, 0);
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si5351c_configure_multisynth(1, p1, 0, 1, 0);//p1 doesn't matter
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/* MS0/CLK2 is the source for SGPIO (CODEC_X2_CLK) */
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si5351c_configure_multisynth(2, p1, 0, 1, 0);
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si5351c_configure_multisynth(2, p1, 0, 1, 0);//p1 doesn't matter
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/* MS0/CLK3 is the source for the external clock output. */
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si5351c_configure_multisynth(3, p1, 0, 1, 0);
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//si5351c_configure_multisynth(3, p1, 0, 1, 0); // no clk out
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return true;
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#endif
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@ -186,19 +190,23 @@ void cpu_clock_init(void)
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*/
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/* MS4/CLK4 is the source for the RFFC5071 mixer. */
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si5351c_configure_multisynth(4, 1536, 0, 1, 0); /* 50MHz */
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si5351c_configure_multisynth(4, 16*128-512, 0, 1, 0); /* 800/16 = 50MHz */
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/* MS5/CLK5 is the source for the MAX2837 clock input. */
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si5351c_configure_multisynth(5, 2048, 0, 1, 0); /* 40MHz */
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si5351c_configure_multisynth(5, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */
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/* MS7/CLK7 is the source for the LPC43xx microcontroller. */
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//si5351c_configure_multisynth(7, 8021, 0, 3, 0); /* 12MHz */
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//uint8_t ms7data[] = { 91, 40, 0x0 };
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//si5351c_write(ms7data, sizeof(ms7data));
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#endif
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/* Set to 10 MHz, the common rate between Jellybean and Jawbreaker. */
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sample_rate_set(10000000);
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si5351c_configure_clock_control();
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// soft reset
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uint8_t resetdata[] = { 177, 0xac };
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si5351c_write(resetdata, sizeof(resetdata));
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si5351c_enable_clock_outputs();
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//FIXME disable I2C
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@ -405,6 +413,9 @@ void pin_setup(void) {
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scu_pinmux(SCU_SSP1_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
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scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
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scu_pinmux(SCU_SSP1_SSEL, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
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/* Configure external clock in */
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//scu_pinmux(P4_7, SCU_CLK_IN | SCU_CONF_FUNCTION1);
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}
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void enable_1v8_power(void) {
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@ -87,7 +87,16 @@ void si5351c_disable_oeb_pin_control()
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/* Power down all CLKx */
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void si5351c_power_down_all_clocks()
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{
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uint8_t data[] = { 16, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0xC0, 0xC0 };
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uint8_t data[] = { 16
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, SI5351C_CLK_POWERDOWN
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, SI5351C_CLK_POWERDOWN
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, SI5351C_CLK_POWERDOWN
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, SI5351C_CLK_POWERDOWN
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, SI5351C_CLK_POWERDOWN
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, SI5351C_CLK_POWERDOWN
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, SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE
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, SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE
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};
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si5351c_write(data, sizeof(data));
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}
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@ -127,8 +136,11 @@ void si5351c_configure_pll_sources_for_xtal()
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/* MultiSynth NA (PLL1) */
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void si5351c_configure_pll1_multisynth()
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{
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//init plla and pllb to (0x0e00+512)/128*25mhz xtal = 800mhz -> int mode
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uint8_t data[] = { 26, 0x00, 0x01, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00 };
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si5351c_write(data, sizeof(data));
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data[0] =34;// pllb
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si5351c_write(data, sizeof(data));
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}
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void si5351c_configure_multisynth(const uint_fast8_t ms_number,
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@ -215,67 +227,25 @@ void si5351c_configure_clock_control()
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#endif
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#ifdef JAWBREAKER
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/*
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* Registers 16 through 23: CLKx Control
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* CLK0:
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* CLK0_PDN=0 (powered up)
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* MS0_INT=1 (integer mode)
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* MS0_SRC=0 (PLLA as source for MultiSynth 0)
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* CLK0_INV=0 (not inverted)
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* CLK0_SRC=3 (MS0 as input source)
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* CLK0_IDRV=3 (8mA)
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* CLK1:
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* CLK1_PDN=0 (powered up)
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* MS1_INT=1 (integer mode)
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* MS1_SRC=0 (PLLA as source for MultiSynth 1)
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* CLK1_INV=0 (not inverted)
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* CLK1_SRC=2 (MS0 as input source)
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* CLK1_IDRV=3 (8mA)
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* CLK2:
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* CLK2_PDN=0 (powered up)
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* MS2_INT=1 (integer mode)
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* MS2_SRC=0 (PLLA as source for MultiSynth 2)
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* CLK2_INV=0 (not inverted)
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* CLK2_SRC=2 (MS0 as input source)
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* CLK2_IDRV=3 (8mA)
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* CLK3:
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* CLK3_PDN=0 (powered up)
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* MS3_INT=1 (integer mode)
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* MS3_SRC=0 (PLLA as source for MultiSynth 3)
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* CLK3_INV=0 (inverted)
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* CLK3_SRC=2 (MS0 as input source)
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* CLK3_IDRV=3 (8mA)
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* CLK4:
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* CLK4_PDN=0 (powered up)
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* MS4_INT=1 (integer mode)
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* MS4_SRC=0 (PLLA as source for MultiSynth 4)
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* CLK4_INV=0 (not inverted)
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* CLK4_SRC=3 (MS4 as input source)
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* CLK4_IDRV=3 (8mA)
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* CLK5:
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* CLK5_PDN=0 (powered up)
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* MS5_INT=1 (integer mode)
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* MS5_SRC=0 (PLLA as source for MultiSynth 5)
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* CLK5_INV=0 (not inverted)
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* CLK5_SRC=3 (MS5 as input source)
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* CLK5_IDRV=3 (8mA)
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* CLK6: (not connected)
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* CLK5_PDN=1 (powered down)
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* MS5_INT=1 (integer mode)
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* CLK7: (not connected)
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* CLK7_PDN=1 (powered down)
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* MS7_INT=0 (fractional mode -- to support 12MHz to LPC)
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*/
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void si5351c_configure_clock_control()
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{
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uint8_t data[] = { 16, 0x4F, 0x4B, 0x4B, 0x4B, 0x4F, 0x4F, 0xC0, 0x80 };
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uint8_t data[] = {16
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,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(SI5351C_CLK_PLL_SRC_B) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA)
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,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(SI5351C_CLK_PLL_SRC_B) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA)
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,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(SI5351C_CLK_PLL_SRC_B) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA)
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,SI5351C_CLK_POWERDOWN /*not connected, clock out*/
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,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(SI5351C_CLK_PLL_SRC_B) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA)
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,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(SI5351C_CLK_PLL_SRC_B) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA)
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,SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/
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,SI5351C_CLK_INT_MODE/* pllb int mode*/| SI5351C_CLK_PLL_SRC(SI5351C_CLK_PLL_SRC_A) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA)
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};
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si5351c_write(data, sizeof(data));
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}
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#endif
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/* Enable CLK outputs 0, 1, 2, 3, 4, 5 only. */
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/* Enable CLK outputs 0, 1, 2, 4, 5, 7 only. */
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void si5351c_enable_clock_outputs()
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{
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uint8_t data[] = { 3, 0xC0 };
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uint8_t data[] = { 3, 0x48 };
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si5351c_write(data, sizeof(data));
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}
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@ -30,8 +30,30 @@ extern "C"
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#include <stdint.h>
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#define SI_INTDIV(x) (x*128-512)
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#define SI5351C_I2C_ADDR (0x60 << 1)
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#define SI5351C_CLK_POWERDOWN (1<<7)
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#define SI5351C_CLK_INT_MODE (1<<6)
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#define SI5351C_CLK_PLL_SRC(x) (x<<5)
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#define SI5351C_CLK_PLL_SRC_A 0
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#define SI5351C_CLK_PLL_SRC_B 1
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#define SI5351C_CLK_INV (1<<4)
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#define SI5351C_CLK_SRC(x) (x<<2)
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#define SI5351C_CLK_SRC_XTAL 0
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#define SI5351C_CLK_SRC_CLKIN 1
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#define SI5351C_CLK_SRC_MULTISYNTH_0_4 2
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#define SI5351C_CLK_SRC_MULTISYNTH_SELF 3
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#define SI5351C_CLK_IDRV(x) (x<<0)
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#define SI5351C_CLK_IDRV_2MA 0
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#define SI5351C_CLK_IDRV_4MA 1
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#define SI5351C_CLK_IDRV_6MA 2
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#define SI5351C_CLK_IDRV_8MA 3
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void si5351c_disable_all_outputs();
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void si5351c_disable_oeb_pin_control();
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void si5351c_power_down_all_clocks();
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