diff --git a/firmware/common/hackrf_core.c b/firmware/common/hackrf_core.c
index 1441394f..3de6dc15 100644
--- a/firmware/common/hackrf_core.c
+++ b/firmware/common/hackrf_core.c
@@ -319,9 +319,10 @@ void cpu_clock_init(void)
  	/* MS5/CLK5 is the source for the MAX2837 clock input. */
 	si5351c_configure_multisynth(5, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */
 
+	/* MS6/CLK6 is unused. */
 	/* MS7/CLK7 is the source for the LPC43xx microcontroller. */
-	//uint8_t ms7data[] = { 91, 40, 0x0 };
-	//si5351c_write(ms7data, sizeof(ms7data));
+	uint8_t ms7data[] = { 90, 255, 20, 0 };
+	si5351c_write(ms7data, sizeof(ms7data));
 #endif
 
 	/* Set to 10 MHz, the common rate between Jellybean and Jawbreaker. */
diff --git a/firmware/common/si5351c.c b/firmware/common/si5351c.c
index d90559cb..6ddac500 100644
--- a/firmware/common/si5351c.c
+++ b/firmware/common/si5351c.c
@@ -237,16 +237,16 @@ void si5351c_configure_clock_control()
 	,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(SI5351C_CLK_PLL_SRC_A) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA)
 	,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(SI5351C_CLK_PLL_SRC_A) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA)
 	,SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/
-	,SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE /* pllb int mode*/| SI5351C_CLK_PLL_SRC(SI5351C_CLK_PLL_SRC_B) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA)
+	,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(SI5351C_CLK_PLL_SRC_A) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA)
 	 };
 	si5351c_write(data, sizeof(data));
 }
 #endif
 
-/* Enable CLK outputs 0, 1, 2, 4, 5, ~7 only. */
+/* Enable CLK outputs 0, 1, 2, 4, 5, 7 only. */
  void si5351c_enable_clock_outputs()
  {
-	uint8_t data[] = { 3, 0xC8 };
+	uint8_t data[] = { 3, 0x48 };
  	si5351c_write(data, sizeof(data));
  }