diff --git a/doc/LPC4330_SGPIO_SignalGenerator_Measurements.ods b/doc/LPC4330_SGPIO_SignalGenerator_Measurements.ods
new file mode 100644
index 00000000..556fb049
Binary files /dev/null and b/doc/LPC4330_SGPIO_SignalGenerator_Measurements.ods differ
diff --git a/doc/LPC4330_SGPIO_SignalGenerator_Measurements.pdf b/doc/LPC4330_SGPIO_SignalGenerator_Measurements.pdf
new file mode 100644
index 00000000..b6ffda5f
Binary files /dev/null and b/doc/LPC4330_SGPIO_SignalGenerator_Measurements.pdf differ
diff --git a/firmware/common/hackrf_core.c b/firmware/common/hackrf_core.c
index c6efb1dc..5f312bee 100644
--- a/firmware/common/hackrf_core.c
+++ b/firmware/common/hackrf_core.c
@@ -231,7 +231,7 @@ void cpu_clock_init(void)
 			| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_XTAL);
 
 	/* use XTAL_OSC as clock source for PLL1 */
-	/* Start PLL1 at 12MHz * 17 / 2 = 102MHz. */
+	/* Start PLL1 at 12MHz * 17 / (2+2) = 51MHz. */
 	CGU_PLL1_CTRL = CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL)
             | CGU_PLL1_CTRL_PSEL(1)
             | CGU_PLL1_CTRL_NSEL(0)
@@ -249,7 +249,8 @@ void cpu_clock_init(void)
 	CGU_PLL1_CTRL = CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL)
             | CGU_PLL1_CTRL_PSEL(0)
             | CGU_PLL1_CTRL_NSEL(0)
-			| CGU_PLL1_CTRL_MSEL(16);
+			| CGU_PLL1_CTRL_MSEL(16)
+			| CGU_PLL1_CTRL_FBSEL;
 
 	/* wait until stable */
 	while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK));