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More tweaks related to CGU #define changes.

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This commit is contained in:
Jared Boone
2012-09-27 17:55:54 -07:00
parent f574f70a87
commit 776c502628
1 changed files with 14 additions and 14 deletions
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28
firmware/common/hackrf_core.c
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@ -142,11 +142,11 @@ void cpu_clock_init(void)
CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_ENABLE;
/* use XTAL_OSC as clock source for BASE_M4_CLK (CPU) */
CGU_BASE_M4_CLK = ((CGU_SRC_XTAL << CGU_BASE_CLK_SEL_SHIFT));
CGU_BASE_M4_CLK = CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_XTAL);
/* use XTAL_OSC as clock source for APB1 */
CGU_BASE_APB1_CLK = (CGU_BASE_CLK_AUTOBLOCK
| (CGU_SRC_XTAL << CGU_BASE_CLK_SEL_SHIFT));
CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK
| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_XTAL);
/* use XTAL_OSC as clock source for PLL1 */
CGU_PLL1_CTRL = (CGU_PLL1_CTRL_AUTOBLOCK
@ -172,21 +172,21 @@ void cpu_clock_init(void)
while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK));
/* use PLL1 as clock source for BASE_M4_CLK (CPU) */
CGU_BASE_M4_CLK = ((CGU_SRC_PLL1 << CGU_BASE_CLK_SEL_SHIFT));
CGU_BASE_M4_CLK = CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_PLL1);
/* use XTAL_OSC as clock source for PLL0USB */
CGU_PLL0USB_CTRL = (CGU_PLL0USB_CTRL_PD
CGU_PLL0USB_CTRL = CGU_PLL0USB_CTRL_PD
| CGU_PLL0USB_CTRL_AUTOBLOCK
| (CGU_SRC_XTAL << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT));
| CGU_PLL0USB_CTRL_CLK_SEL(CGU_SRC_XTAL);
while (CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK);
/* configure PLL0USB to produce 480 MHz clock from 12 MHz XTAL_OSC */
CGU_PLL0USB_MDIV = ((0x07FFA << CGU_PLL0USB_MDIV_MDEC_SHIFT)
| (0x0B << CGU_PLL0USB_SELP_MDEC_SHIFT)
| (0x10 << CGU_PLL0USB_SELI_MDEC_SHIFT)
| (0x0 << CGU_PLL0USB_SELR_MDEC_SHIFT));
CGU_PLL0USB_NP_DIV = (98 << CGU_PLL0USB_NP_DIV_PDEC_SHIFT)
| (514 << CGU_PLL0USB_NP_DIV_NDEC_SHIFT);
CGU_PLL0USB_MDIV = CGU_PLL0USB_MDIV_MDEC(0x07FFA)
| CGU_PLL0USB_MDIV_SELP(0x0B)
| CGU_PLL0USB_MDIV_SELI(0x10)
| CGU_PLL0USB_MDIV_SELR(0x0);
CGU_PLL0USB_NP_DIV = CGU_PLL0USB_NP_DIV_PDEC(98)
| CGU_PLL0USB_NP_DIV_NDEC(514);
CGU_PLL0USB_CTRL |= (CGU_PLL0USB_CTRL_PD
| CGU_PLL0USB_CTRL_DIRECTI
| CGU_PLL0USB_CTRL_DIRECTO
@ -197,8 +197,8 @@ void cpu_clock_init(void)
while (!(CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK));
/* use PLL0USB as clock source for USB0 */
CGU_BASE_USB0_CLK = (CGU_BASE_CLK_AUTOBLOCK
| (CGU_SRC_PLL0USB << CGU_BASE_CLK_SEL_SHIFT));
CGU_BASE_USB0_CLK = CGU_BASE_USB0_CLK_AUTOBLOCK
| CGU_BASE_USB0_CLK_CLK_SEL(CGU_SRC_PLL0USB);
}
void ssp1_init(void)