From 63b1a25979b4aff0d12eb55316b5b5066e5373a3 Mon Sep 17 00:00:00 2001
From: Jared Boone <jboone@earfeast.com>
Date: Wed, 17 Oct 2012 11:45:30 -0700
Subject: [PATCH] Consolidate a few clock setup tasks that repeat among many
 projects into cpu_clock_init().

---
 firmware/common/hackrf_core.c                             | 8 ++++++++
 firmware/sgpio-rx/sgpio-rx.c                              | 7 -------
 firmware/sgpio/sgpio.c                                    | 6 ------
 firmware/sgpio_passthrough_rom_to_ram/sgpio_passthrough.c | 7 -------
 firmware/usb_performance/usb_performance.c                | 6 ------
 5 files changed, 8 insertions(+), 26 deletions(-)

diff --git a/firmware/common/hackrf_core.c b/firmware/common/hackrf_core.c
index 3bca88df..fd3cd70b 100644
--- a/firmware/common/hackrf_core.c
+++ b/firmware/common/hackrf_core.c
@@ -194,6 +194,14 @@ void cpu_clock_init(void)
 	/* use PLL0USB as clock source for USB0 */
 	CGU_BASE_USB0_CLK = CGU_BASE_USB0_CLK_AUTOBLOCK
 			| CGU_BASE_USB0_CLK_CLK_SEL(CGU_SRC_PLL0USB);
+
+	/* Switch peripheral clock over to use PLL1 (204MHz) */
+	CGU_BASE_PERIPH_CLK = CGU_BASE_PERIPH_CLK_AUTOBLOCK
+			| CGU_BASE_PERIPH_CLK_CLK_SEL(CGU_SRC_PLL1);
+
+	/* Switch APB1 clock over to use PLL1 (204MHz) */
+	CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK
+			| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_PLL1);
 }
 
 void ssp1_init(void)
diff --git a/firmware/sgpio-rx/sgpio-rx.c b/firmware/sgpio-rx/sgpio-rx.c
index 62f29988..a9270a5c 100644
--- a/firmware/sgpio-rx/sgpio-rx.c
+++ b/firmware/sgpio-rx/sgpio-rx.c
@@ -96,13 +96,6 @@ int main(void) {
 	pin_setup();
 	enable_1v8_power();
 	cpu_clock_init();
-
-	CGU_BASE_PERIPH_CLK = CGU_BASE_PERIPH_CLK_AUTOBLOCK
-			| CGU_BASE_PERIPH_CLK_CLK_SEL(CGU_SRC_PLL1);
-
-	CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK
-			| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_PLL1);
-	
     ssp1_init();
 	ssp1_set_mode_max2837();
 	max2837_setup();
diff --git a/firmware/sgpio/sgpio.c b/firmware/sgpio/sgpio.c
index fbf40ffd..e298c93e 100644
--- a/firmware/sgpio/sgpio.c
+++ b/firmware/sgpio/sgpio.c
@@ -72,12 +72,6 @@ int main(void) {
 	cpu_clock_init();
 	ssp1_init();
 
-	CGU_BASE_PERIPH_CLK = CGU_BASE_PERIPH_CLK_AUTOBLOCK
-			| CGU_BASE_PERIPH_CLK_CLK_SEL(CGU_SRC_PLL1);
-
-	CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK
-			| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_PLL1);
-
 	gpio_set(PORT_LED1_3, PIN_LED1);
 
 	ssp1_set_mode_max5864();
diff --git a/firmware/sgpio_passthrough_rom_to_ram/sgpio_passthrough.c b/firmware/sgpio_passthrough_rom_to_ram/sgpio_passthrough.c
index afdf8a25..561aaa9d 100644
--- a/firmware/sgpio_passthrough_rom_to_ram/sgpio_passthrough.c
+++ b/firmware/sgpio_passthrough_rom_to_ram/sgpio_passthrough.c
@@ -354,13 +354,6 @@ int main(void)
 	enable_1v8_power();
 	cpu_clock_init();
 	ssp1_init();
-
-	CGU_BASE_PERIPH_CLK = (CGU_BASE_CLK_AUTOBLOCK
-			| (CGU_SRC_PLL1 << CGU_BASE_CLK_SEL_SHIFT));
-
-	CGU_BASE_APB1_CLK = (CGU_BASE_CLK_AUTOBLOCK
-			| (CGU_SRC_PLL1 << CGU_BASE_CLK_SEL_SHIFT));
-
 	gpio_set(PORT_LED1_3, PIN_LED1);
 
 	//test_sgpio_sliceA_D();
diff --git a/firmware/usb_performance/usb_performance.c b/firmware/usb_performance/usb_performance.c
index 88766176..32e3beef 100644
--- a/firmware/usb_performance/usb_performance.c
+++ b/firmware/usb_performance/usb_performance.c
@@ -394,12 +394,6 @@ int main(void) {
 	enable_1v8_power();
 	cpu_clock_init();
 
-	CGU_BASE_PERIPH_CLK = CGU_BASE_PERIPH_CLK_AUTOBLOCK
-			| CGU_BASE_PERIPH_CLK_CLK_SEL(CGU_SRC_PLL1);
-
-	CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK
-			| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_PLL1);
-	
 	usb_peripheral_reset();
 	
 	usb_device_init(0, &usb_device);