schematic notes
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EESchema Schematic File Version 2 date Wed Sep 5 10:36:00 2012
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EESchema Schematic File Version 2 date Wed Sep 5 10:46:14 2012
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LIBS:power
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LIBS:device
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LIBS:transistors
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EESchema Schematic File Version 2 date Wed Sep 5 10:36:00 2012
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EESchema Schematic File Version 2 date Wed Sep 5 10:46:14 2012
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LIBS:power
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LIBS:device
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LIBS:transistors
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EESchema-LIBRARY Version 2.3 Date: Wed Sep 5 10:36:00 2012
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EESchema-LIBRARY Version 2.3 Date: Wed Sep 5 10:46:14 2012
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#encoding utf-8
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#
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# +1.8V
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EESchema Schematic File Version 2 date Wed Sep 5 10:36:00 2012
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EESchema Schematic File Version 2 date Wed Sep 5 10:46:14 2012
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LIBS:power
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LIBS:device
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LIBS:transistors
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@ -1,4 +1,4 @@
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EESchema Schematic File Version 2 date Wed Sep 5 10:36:00 2012
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EESchema Schematic File Version 2 date Wed Sep 5 10:46:14 2012
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LIBS:power
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LIBS:device
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LIBS:transistors
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@ -45,6 +45,10 @@ Comment2 ""
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Comment3 ""
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Comment4 ""
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$EndDescr
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Text Notes 8250 1400 0 40 ~ 0
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traces may be cut to install\nheader and jumpers
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Text Notes 12000 9550 0 40 ~ 0
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R97 may be installed to connect SGPIO8 to the CPLD.\nBy default SGPIO8 is used as a clock input.
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NoConn ~ 9700 5800
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Text GLabel 8750 7750 3 40 Input ~ 0
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SGPIO_CLK
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