diff --git a/hardware/jellybean/sgpio_if/README.md b/hardware/jellybean/sgpio_if/README.md
index 2f9a062e..f225f37b 100644
--- a/hardware/jellybean/sgpio_if/README.md
+++ b/hardware/jellybean/sgpio_if/README.md
@@ -1,4 +1,3 @@
-
 CPLD interface between LPC43xx microcontroller SGPIO peripheral and MAX5864
 RF codec.
 
@@ -9,12 +8,6 @@ To build this VHDL project and produce an SVF file for flashing the CPLD:
 
 * Xilinx WebPACK 13.4 for Windows or Linux.
 
-* BSDL model files for Xilinx CoolRunner-II XC264A, available at xilinx.com,
-  in the "Device Models" Support Resources section of the CoolRunner-II
-  Product Support & Documentation page. Only one file from the BSDL package is
-  required, and the "program" script below expects it to be at the relative
-  path "bsdl/xc2c/xc2c64.bsd".
-
 To program the SVF file into the CPLD:
 
 * Dangerous Prototypes Bus Blaster v2:
@@ -23,6 +16,12 @@ To program the SVF file into the CPLD:
 
 * urJTAG built with libftdi support.
 
+* BSDL model files for Xilinx CoolRunner-II XC264A, available at xilinx.com,
+  in the "Device Models" Support Resources section of the CoolRunner-II
+  Product Support & Documentation page. Only one file from the BSDL package is
+  required, and the "program" script below expects it to be at the relative
+  path "bsdl/xc2c/xc2c64.bsd".
+
 To Program
 ==========