From 5fe57e0238e9165511f37b2493b507f365640183 Mon Sep 17 00:00:00 2001
From: Michael Ossmann <mike@ossmann.com>
Date: Wed, 6 Jun 2012 21:26:16 -0600
Subject: [PATCH] clock setup code ported from Jared

---
 firmware/common/jellybean.c | 77 ++++++++++++++++++++++++++++++++++++-
 1 file changed, 76 insertions(+), 1 deletion(-)

diff --git a/firmware/common/jellybean.c b/firmware/common/jellybean.c
index 2cfc03a4..dca090e3 100644
--- a/firmware/common/jellybean.c
+++ b/firmware/common/jellybean.c
@@ -22,6 +22,14 @@
 
 #include "si5351c.h"
 
+void delay(uint32_t duration)
+{
+	uint32_t i;
+
+	for (i = 0; i < duration; i++)
+		__asm__("nop");
+}
+
 /* initial configuration for Jellybean with Lemondrop attached */ 
 void jellybean_init(void)
 {
@@ -54,5 +62,72 @@ void jellybean_init(void)
 	 * Set up PLL1 to run from XTAL1 input.
 	 */
 
-	//FIXME CGU setup
+	//FIXME a lot of the details here should be in a CGU driver
+
+	/* configure xtal oscillator for external clock input signal */
+	CGU_XTAL_OSC_CTRL |= CGU_XTAL_OSC_CTRL_BYPASS;
+
+	/* set xtal oscillator to low frequency mode */
+	CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_HF;
+
+	/* power on the oscillator and wait until stable */
+	CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_EN;
+	delay(1000000);
+
+	/* use XTAL_OSC as clock source for BASE_M4_CLK (CPU) */
+	CGU_BASE_M4_CLK = (CGU_BASE_CLK_AUTOBLOCK
+			| (CGU_SRC_XTAL << CGU_BASE_CLK_SEL_SHIFT));
+
+	/* use XTAL_OSC as clock source for APB1 */
+	CGU_BASE_APB1_CLK = (CGU_BASE_CLK_AUTOBLOCK
+			| (CGU_SRC_XTAL << CGU_BASE_CLK_SEL_SHIFT));
+
+	/* use XTAL_OSC as clock source for PLL1 */
+	CGU_PLL1_CTRL = (CGU_PLL1_CTRL_PD
+			| CGU_PLL1_CTRL_AUTOBLOCK
+			| (CGU_SRC_XTAL << CGU_PLL1_CTRL_CLK_SEL_SHIFT));
+	while (CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK);
+
+	//FIXME this may need to be done in several stages
+	/* configure PLL1 to produce 204 MHz clock from 12 MHz XTAL_OSC */
+	CGU_PLL1_CTRL |= (CGU_PLL1_CTRL_PD
+			| CGU_PLL1_CTRL_FBSEL
+			| CGU_PLL1_CTRL_DIRECT
+			| (0 << CGU_PLL1_CTRL_PSEL_SHIFT)
+			| (0 << CGU_PLL1_CTRL_NSEL_SHIFT)
+			| (16 << CGU_PLL1_CTRL_MSEL_SHIFT));
+
+	/* power on PLL1 and wait until stable */
+	CGU_PLL1_CTRL &= ~CGU_PLL1_CTRL_PD;
+	while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK));
+
+	/* use PLL1 as clock source for BASE_M4_CLK (CPU) */
+	CGU_BASE_M4_CLK = (CGU_BASE_CLK_AUTOBLOCK
+			| (CGU_SRC_PLL1 << CGU_BASE_CLK_SEL_SHIFT));
+
+	/* use XTAL_OSC as clock source for PLL0USB */
+	CGU_PLL0USB_CTRL = (CGU_PLL0USB_CTRL_PD
+			| CGU_PLL0USB_CTRL_AUTOBLOCK
+			| (CGU_SRC_XTAL << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT));
+	while (CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK);
+
+	/* configure PLL0USB to produce 480 MHz clock from 12 MHz XTAL_OSC */
+	CGU_PLL0USB_MDIV = ((0x07FFA << CGU_PLL0USB_MDIV_MDEC_SHIFT)
+			| (0x0B << CGU_PLL0USB_SELP_MDEC_SHIFT)
+			| (0x10 << CGU_PLL0USB_SELI_MDEC_SHIFT)
+			| (0x0 << CGU_PLL0USB_SELR_MDEC_SHIFT));
+	CGU_PLL0USB_NP_DIV = (98 << CGU_PLL0USB_NP_DIV_PDEC_SHIFT)
+			| (514 << CGU_PLL0USB_NP_DIV_NDEC_SHIFT);
+	CGU_PLL0USB_CTRL |= (CGU_PLL0USB_CTRL_PD
+			| CGU_PLL0USB_CTRL_DIRECTI
+			| CGU_PLL0USB_CTRL_DIRECTO
+			| CGU_PLL0USB_CTRL_CLKEN);
+
+	/* power on PLL0USB and wait until stable */
+	CGU_PLL0USB_CTRL &= ~CGU_PLL0USB_CTRL_PD;
+	while (!(CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK));
+
+	/* use PLL0USB as clock source for USB0 */
+	CGU_BASE_USB0_CLK = (CGU_BASE_CLK_AUTOBLOCK
+			| (CGU_SRC_PLL0USB << CGU_BASE_CLK_SEL_SHIFT));
 }