diff --git a/firmware/cpld/sgpio_if/sgpio_if.xise b/firmware/cpld/sgpio_if/sgpio_if.xise
index 82c5ad11..500e07da 100755
--- a/firmware/cpld/sgpio_if/sgpio_if.xise
+++ b/firmware/cpld/sgpio_if/sgpio_if.xise
@@ -9,10 +9,10 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="14.1" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="top.vhd" xil_pn:type="FILE_VHDL">