diff --git a/firmware/common/clkin.c b/firmware/common/clkin.c
index 1d8e7511..5ab8123a 100644
--- a/firmware/common/clkin.c
+++ b/firmware/common/clkin.c
@@ -49,35 +49,32 @@ tcr_sequence reset;
 
 void clkin_detect_init(void)
 {
-	/* Timer3 triggers periodic measurement */
-	timer_set_prescaler(TIMER3, 0);
-	timer_set_mode(TIMER3, TIMER_CTCR_MODE_TIMER);
-	TIMER3_MCR = TIMER_MCR_MR0R;
-	TIMER3_EMR = (TIMER_EMR_EMC_SET << TIMER_EMR_EMC0_SHIFT) |
+	/* Timer1 triggers periodic measurement */
+	timer_set_prescaler(TIMER1, 0);
+	timer_set_mode(TIMER1, TIMER_CTCR_MODE_TIMER);
+	TIMER1_MCR = TIMER_MCR_MR0R;
+	TIMER1_EMR = (TIMER_EMR_EMC_SET << TIMER_EMR_EMC0_SHIFT) |
 		(TIMER_EMR_EMC_TOGGLE << TIMER_EMR_EMC3_SHIFT);
-	TIMER3_MR3 = MEASUREMENT_CYCLES;
-	TIMER3_MR0 = MEASUREMENT_CYCLES;
+	TIMER1_MR3 = MEASUREMENT_CYCLES;
+	TIMER1_MR0 = MEASUREMENT_CYCLES;
+
+	/* prevent TIMER1_MR3 from interfering with SCT */
 	CREG_CREG6 |= CREG_CREG6_CTOUTCTRL;
 
-	/* Timer0 counts CLKIN */
-	timer_set_prescaler(TIMER0, 0);
-	TIMER0_CCR = TIMER_CCR_CAP3RE;
-	GIMA_CAP0_3_IN = 0x20; // T3_MAT3
+	/* Timer2 counts CLKIN */
+	timer_set_prescaler(TIMER2, 0);
+	TIMER2_CCR = TIMER_CCR_CAP3RE;
+	GIMA_CAP2_3_IN = 0x20; // T1_MAT3
 
-	/* measure CLKIN signal on P2_5, pin 91, CTIN_2 */
-	TIMER0_CTCR = TIMER_CTCR_MODE_COUNTER_RISING | TIMER_CTCR_CINSEL_CAPN_2;
-	scu_pinmux(P2_5, SCU_GPIO_PDN | SCU_CONF_FUNCTION1);
-	GIMA_CAP0_2_IN = 0x00; // CTIN_2
-
-	// temporarily testing with T0_CAP1, P1_12, pin 56, P28 pin 4
-	//TIMER0_CTCR = TIMER_CTCR_MODE_COUNTER_RISING | TIMER_CTCR_CINSEL_CAPN_1;
-	//scu_pinmux(P1_12, SCU_GPIO_PDN | SCU_CONF_FUNCTION4);
-	//GIMA_CAP0_1_IN = 0x20; // T0_CAP1
+	/* measure CLKIN_DETECT signal on P4_8, pin 15, CTIN_5 */
+	TIMER2_CTCR = TIMER_CTCR_MODE_COUNTER_RISING | TIMER_CTCR_CINSEL_CAPN_2;
+	scu_pinmux(P4_8, SCU_GPIO_PDN | SCU_CONF_FUNCTION1); // CTIN_5
+	GIMA_CAP2_2_IN = 0x00;                               // CTIN_5
 
 	reset.first_tcr = TIMER_TCR_CEN | TIMER_TCR_CRST;
 	reset.second_tcr = TIMER_TCR_CEN;
 	timer_dma_lli.src = (uint32_t) & (reset);
-	timer_dma_lli.dest = (uint32_t) & (TIMER0_TCR);
+	timer_dma_lli.dest = (uint32_t) & (TIMER2_TCR);
 	timer_dma_lli.next_lli = (uint32_t) & (timer_dma_lli);
 	timer_dma_lli.control = GPDMA_CCONTROL_TRANSFERSIZE(2) |
 		GPDMA_CCONTROL_SBSIZE(0)   // 1
@@ -97,19 +94,19 @@ void clkin_detect_init(void)
 	GPDMA_C0DESTADDR = timer_dma_lli.dest;
 	GPDMA_C0LLI = timer_dma_lli.next_lli;
 	GPDMA_C0CONTROL = timer_dma_lli.control;
-	GPDMA_C0CONFIG = GPDMA_CCONFIG_DESTPERIPHERAL(0x7) // T3_MAT0
+	GPDMA_C0CONFIG = GPDMA_CCONFIG_DESTPERIPHERAL(0x3) // T1_MAT0
 		| GPDMA_CCONFIG_FLOWCNTRL(1)               // memory-to-peripheral
 		| GPDMA_CCONFIG_H(0);                      // do not halt
 	gpdma_channel_enable(0);
 
 	/* start counting */
-	timer_reset(TIMER0);
-	timer_reset(TIMER3);
-	timer_enable_counter(TIMER0);
-	timer_enable_counter(TIMER3);
+	timer_reset(TIMER2);
+	timer_reset(TIMER1);
+	timer_enable_counter(TIMER2);
+	timer_enable_counter(TIMER1);
 }
 
 uint32_t clkin_frequency(void)
 {
-	return TIMER0_CR3 * (1000 / MEASUREMENT_WINDOW_MS);
+	return TIMER2_CR3 * (1000 / MEASUREMENT_WINDOW_MS);
 };
diff --git a/firmware/common/hackrf_core.c b/firmware/common/hackrf_core.c
index a88e1695..b5acb892 100644
--- a/firmware/common/hackrf_core.c
+++ b/firmware/common/hackrf_core.c
@@ -144,9 +144,10 @@ static struct gpio_t gpio_rx_q_invert       = GPIO(0, 13);
 
 /* HackRF One r9 */
 #ifdef HACKRF_ONE
-static struct gpio_t gpio_h1r9_rx            = GPIO(0,  7);
-static struct gpio_t gpio_h1r9_no_rx_amp_pwr = GPIO(3,  6);
-static struct gpio_t gpio_h1r9_1v8_enable    = GPIO(1, 12);
+static struct gpio_t gpio_h1r9_rx             = GPIO(0, 7);
+static struct gpio_t gpio_h1r9_1v8_enable     = GPIO(2, 9);
+static struct gpio_t gpio_h1r9_vaa_disable    = GPIO(3, 6);
+static struct gpio_t gpio_h1r9_hw_sync_enable = GPIO(5, 5);
 #endif
 // clang-format on
 
@@ -829,10 +830,10 @@ void cpu_clock_init(void)
 	// CCU1_CLK_M4_SCT_CFG = 0;
 	CCU1_CLK_M4_SDIO_CFG = 0;
 	CCU1_CLK_M4_SPIFI_CFG = 0;
-	//CCU1_CLK_M4_TIMER0_CFG = 0;
-	CCU1_CLK_M4_TIMER1_CFG = 0;
-	CCU1_CLK_M4_TIMER2_CFG = 0;
-	//CCU1_CLK_M4_TIMER3_CFG = 0;
+	CCU1_CLK_M4_TIMER0_CFG = 0;
+	//CCU1_CLK_M4_TIMER1_CFG = 0;
+	//CCU1_CLK_M4_TIMER2_CFG = 0;
+	CCU1_CLK_M4_TIMER3_CFG = 0;
 	CCU1_CLK_M4_UART1_CFG = 0;
 	CCU1_CLK_M4_USART0_CFG = 0;
 	CCU1_CLK_M4_USART2_CFG = 0;
@@ -960,7 +961,7 @@ void pin_setup(void)
 	if (detected_platform() == BOARD_ID_HACKRF1_R9) {
 #ifdef HACKRF_ONE
 		gpio_output(&gpio_h1r9_1v8_enable);
-		scu_pinmux(P2_12, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
+		scu_pinmux(SCU_H1R9_EN1V8, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
 #endif
 	} else {
 		gpio_output(&gpio_1v8_enable);
@@ -972,7 +973,11 @@ void pin_setup(void)
 	disable_rf_power();
 
 	/* Configure RF power supply (VAA) switch control signal as output */
-	gpio_output(&gpio_vaa_disable);
+	if (detected_platform() == BOARD_ID_HACKRF1_R9) {
+		gpio_output(&gpio_h1r9_vaa_disable);
+	} else {
+		gpio_output(&gpio_vaa_disable);
+	}
 #endif
 
 #ifdef RAD1O
@@ -1005,7 +1010,7 @@ void pin_setup(void)
 #ifdef HACKRF_ONE
 	if (detected_platform() == BOARD_ID_HACKRF1_R9) {
 		rf_path.gpio_rx = &gpio_h1r9_rx;
-		rf_path.gpio_no_rx_amp_pwr = &gpio_h1r9_no_rx_amp_pwr;
+		sgpio_config.gpio_hw_sync_enable = &gpio_h1r9_hw_sync_enable;
 	}
 #endif
 	rf_path_pin_setup(&rf_path);
@@ -1045,15 +1050,23 @@ void enable_rf_power(void)
 
 	/* many short pulses to avoid one big voltage glitch */
 	for (i = 0; i < 1000; i++) {
-		gpio_clear(&gpio_vaa_disable);
-		gpio_set(&gpio_vaa_disable);
+		if (detected_platform() == BOARD_ID_HACKRF1_R9) {
+			gpio_set(&gpio_h1r9_vaa_disable);
+			gpio_clear(&gpio_h1r9_vaa_disable);
+		} else {
+			gpio_set(&gpio_vaa_disable);
+			gpio_clear(&gpio_vaa_disable);
+		}
 	}
-	gpio_clear(&gpio_vaa_disable);
 }
 
 void disable_rf_power(void)
 {
-	gpio_set(&gpio_vaa_disable);
+	if (detected_platform() == BOARD_ID_HACKRF1_R9) {
+		gpio_set(&gpio_h1r9_vaa_disable);
+	} else {
+		gpio_set(&gpio_vaa_disable);
+	}
 }
 #endif
 
@@ -1100,7 +1113,7 @@ void set_leds(const uint8_t state)
 
 void hw_sync_enable(const hw_sync_mode_t hw_sync_mode)
 {
-	gpio_write(&gpio_hw_sync_enable, hw_sync_mode == 1);
+	gpio_write(sgpio_config.gpio_hw_sync_enable, hw_sync_mode == 1);
 }
 
 void halt_and_flash(const uint32_t duration)
diff --git a/firmware/common/hackrf_core.h b/firmware/common/hackrf_core.h
index 8045b1d2..0bd22da0 100644
--- a/firmware/common/hackrf_core.h
+++ b/firmware/common/hackrf_core.h
@@ -109,9 +109,9 @@ extern "C" {
 #define SCU_PINMUX_SGPIO10 (P1_14)
 #define SCU_PINMUX_SGPIO11 (P1_17)
 #define SCU_PINMUX_SGPIO12 (P1_18)
-#define SCU_PINMUX_SGPIO13 (P4_8)
 #define SCU_PINMUX_SGPIO14 (P4_9)
 #define SCU_PINMUX_SGPIO15 (P4_10)
+#define SCU_HW_SYNC_EN     (P4_8) /* GPIO5[12] on P4_8 */
 
 /* MAX2837 GPIO (XCVR_CTL) PinMux */
 #ifdef RAD1O
@@ -234,12 +234,14 @@ extern "C" {
 #define SCU_PINMUX_GP_CLKIN (P4_7)
 
 /* HackRF One r9 */
-#define SCU_H1R9_CLKIN_EN      (P6_7)  /* GPIO5[15] on P6_7 */
-#define SCU_H1R9_CLKOUT_EN     (P1_2)  /* GPIO0[9] on P1_2 (has boot pull-down) */
-#define SCU_H1R9_MCU_CLK_EN    (P1_1)  /* GPIO0[8] on P1_1 (has boot pull-up) */
-#define SCU_H1R9_RX            (P2_7)  /* GPIO0[7] on P4_4 (has boot pull-up) */
-#define SCU_H1R9_NO_RX_AMP_PWR (P6_10) /* GPIO3[6] on P6_10 */
-#define SCU_H1R9_NO_ANT_PWR    (P4_4)  /* GPIO2[4] on P4_4 */
+#define SCU_H1R9_CLKIN_EN   (P6_7)  /* GPIO5[15] on P6_7 */
+#define SCU_H1R9_CLKOUT_EN  (P1_2)  /* GPIO0[9] on P1_2 (has boot pull-down) */
+#define SCU_H1R9_MCU_CLK_EN (P1_1)  /* GPIO0[8] on P1_1 (has boot pull-up) */
+#define SCU_H1R9_RX         (P2_7)  /* GPIO0[7] on P4_4 (has boot pull-up) */
+#define SCU_H1R9_NO_ANT_PWR (P4_4)  /* GPIO2[4] on P4_4 */
+#define SCU_H1R9_EN1V8      (P5_0)  /* GPIO2[9] on P5_0 */
+#define SCU_H1R9_NO_VAA_EN  (P6_10) /* GPIO3[6] on P6_10 */
+#define SCU_H1R9_HW_SYNC_EN (P2_5)  /* GPIO5[5] on P2_5 */
 
 typedef enum {
 	TRANSCEIVER_MODE_OFF = 0,
diff --git a/firmware/common/platform_detect.c b/firmware/common/platform_detect.c
index 1cc6f479..e1608bd8 100644
--- a/firmware/common/platform_detect.c
+++ b/firmware/common/platform_detect.c
@@ -42,13 +42,13 @@ static struct gpio_t gpio3_6_on_P6_10 = GPIO(3, 6);
  * Jawbreaker has a pull-down on P6_10 and nothing on P5_0.
  * rad1o has a pull-down on P6_10 and a pull-down on P5_0.
  * HackRF One OG has a pull-down on P6_10 and a pull-up on P5_0.
- * HackRF One r9 has a pull-up on P6_10 and a pull-up on P5_0. //FIXME temporary
+ * HackRF One r9 has a pull-up on P6_10 and a pull-down on P5_0.
  */
 
 #define JAWBREAKER_RESISTORS (P6_10_PDN)
 #define RAD1O_RESISTORS      (P6_10_PDN | P5_0_PDN)
 #define HACKRF1_OG_RESISTORS (P6_10_PDN | P5_0_PUP)
-#define HACKRF1_R9_RESISTORS (P6_10_PUP | P5_0_PUP)
+#define HACKRF1_R9_RESISTORS (P6_10_PUP | P5_0_PDN)
 
 /*
  * LEDs are configured so that they flash if the detected hardware platform is
@@ -198,11 +198,6 @@ void detect_hardware_platform(void)
 		(adc0_3 == PIN_STRAP_LOW) && (adc0_4 == PIN_STRAP_LOW) &&
 		(platform == BOARD_ID_HACKRF1_R9)) {
 		revision = BOARD_REV_HACKRF1_R9;
-	} else if ( //FIXME temporary
-		(adc0_3 == PIN_STRAP_LOW) && (adc0_4 == PIN_STRAP_LOW) &&
-		(platform == BOARD_ID_HACKRF1_OG)) {
-		revision = BOARD_REV_HACKRF1_R9;
-		platform = BOARD_ID_HACKRF1_R9;
 	} else {
 		revision = BOARD_REV_UNRECOGNIZED;
 	}
diff --git a/firmware/common/rf_path.c b/firmware/common/rf_path.c
index fc04569e..bdc5341e 100644
--- a/firmware/common/rf_path.c
+++ b/firmware/common/rf_path.c
@@ -286,23 +286,21 @@ void rf_path_pin_setup(rf_path_t* const rf_path)
 	scu_pinmux(SCU_NO_TX_AMP_PWR, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
 	scu_pinmux(SCU_AMP_BYPASS,    SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
 	scu_pinmux(SCU_RX_AMP,        SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
+	scu_pinmux(SCU_NO_RX_AMP_PWR, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
 	// clang-format on
 	if (detected_platform() == BOARD_ID_HACKRF1_R9) {
 		scu_pinmux(SCU_H1R9_RX, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
-		scu_pinmux(SCU_H1R9_NO_RX_AMP_PWR, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
 		scu_pinmux(SCU_H1R9_NO_ANT_PWR, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
 		gpio_clear(&gpio_h1r9_no_ant_pwr);
 		gpio_output(&gpio_h1r9_no_ant_pwr);
+		scu_pinmux(SCU_H1R9_NO_VAA_EN, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
 	} else {
 		scu_pinmux(SCU_TX, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
 		scu_pinmux(SCU_RX, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
-		scu_pinmux(SCU_NO_RX_AMP_PWR, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
 		gpio_output(rf_path->gpio_tx);
+		scu_pinmux(SCU_NO_VAA_ENABLE, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
 	}
 
-	/* Configure RF power supply (VAA) switch */
-	scu_pinmux(SCU_NO_VAA_ENABLE, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
-
 	/*
 	 * Safe (initial) switch settings turn off both amplifiers and antenna port
 	 * power and enable both amp bypass and mixer bypass.
diff --git a/firmware/common/sgpio.c b/firmware/common/sgpio.c
index 5c5728fe..fe0ddce1 100644
--- a/firmware/common/sgpio.c
+++ b/firmware/common/sgpio.c
@@ -49,10 +49,19 @@ void sgpio_configure_pin_functions(sgpio_config_t* const config)
 	scu_pinmux(SCU_PINMUX_SGPIO10, SCU_GPIO_FAST | SCU_CONF_FUNCTION6);
 	scu_pinmux(SCU_PINMUX_SGPIO11, SCU_GPIO_FAST | SCU_CONF_FUNCTION6);
 	scu_pinmux(SCU_PINMUX_SGPIO12, SCU_GPIO_FAST | SCU_CONF_FUNCTION0); /* GPIO0[13] */
-	scu_pinmux(SCU_PINMUX_SGPIO13, SCU_GPIO_FAST | SCU_CONF_FUNCTION4); /* GPIO5[12] */
 	scu_pinmux(SCU_PINMUX_SGPIO14, SCU_GPIO_FAST | SCU_CONF_FUNCTION4); /* GPIO5[13] */
 	scu_pinmux(SCU_PINMUX_SGPIO15, SCU_GPIO_FAST | SCU_CONF_FUNCTION4); /* GPIO5[14] */
 
+	if (detected_platform() == BOARD_ID_HACKRF1_R9) {
+		scu_pinmux(
+			SCU_H1R9_HW_SYNC_EN,
+			SCU_GPIO_FAST | SCU_CONF_FUNCTION4); /* GPIO5[5] */
+	} else {
+		scu_pinmux(
+			SCU_HW_SYNC_EN,
+			SCU_GPIO_FAST | SCU_CONF_FUNCTION4); /* GPIO5[12] */
+	}
+
 	sgpio_cpld_stream_rx_set_q_invert(config, 0);
 	hw_sync_enable(0);