LPC4320 placed

This commit is contained in:
Michael Ossmann
2013-11-01 16:53:22 -06:00
parent 52c7f3297b
commit 4af6b1688b
5 changed files with 6319 additions and 6993 deletions

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@ -1,4 +1,4 @@
EESchema-LIBRARY Version 2.3 Date: Thu Oct 31 23:42:52 2013 EESchema-LIBRARY Version 2.3 Date: Fri Nov 1 15:08:23 2013
#encoding utf-8 #encoding utf-8
# #
# +1.8V # +1.8V

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@ -1,4 +1,4 @@
Cmp-Mod V01 Created by CvPcb (2013-07-24 BZR 4024)-stable date = Thu Oct 31 23:43:07 2013 Cmp-Mod V01 Created by CvPcb (2013-07-24 BZR 4024)-stable date = Fri Nov 1 15:08:32 2013
BeginCmp BeginCmp
TimeStamp = /503BB638/4FAECB99; TimeStamp = /503BB638/4FAECB99;
@ -1988,13 +1988,6 @@ ValeurCmp = 39;
IdModule = GSG-0402; IdModule = GSG-0402;
EndCmp EndCmp
BeginCmp
TimeStamp = /5037043E/503F98AA;
Reference = R97;
ValeurCmp = 39;
IdModule = GSG-0402;
EndCmp
BeginCmp BeginCmp
TimeStamp = /5037043E/503F98AC; TimeStamp = /5037043E/503F98AC;
Reference = R98; Reference = R98;

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@ -191,8 +191,6 @@ F 6 "RES 10K OHM 1/16W 5% 0402 SMD" H 1250 9400 60 0001 C CNN "Description"
$EndComp $EndComp
Text Notes 2200 9200 0 40 ~ 0 Text Notes 2200 9200 0 40 ~ 0
Default boot configuration is SPIFI.\nPress SW1 during reset to switch to\nUSB0 (DFU mode). Default boot configuration is SPIFI.\nPress SW1 during reset to switch to\nUSB0 (DFU mode).
Text Notes 12000 9550 0 40 ~ 0
R97 may be installed to connect SGPIO8 to the CPLD.\nBy default SGPIO8 is used as a clock input.
Text GLabel 8750 7750 3 40 Input ~ 0 Text GLabel 8750 7750 3 40 Input ~ 0
SGPIO_CLK SGPIO_CLK
$Comp $Comp
@ -280,10 +278,6 @@ Text Label 16000 6550 2 40 ~ 0
BANK2F3M14 BANK2F3M14
Text Label 11850 10000 2 40 ~ 0 Text Label 11850 10000 2 40 ~ 0
BANK2F3M14 BANK2F3M14
Text Label 16000 6450 2 40 ~ 0
BANK2F3M13
Text Label 11850 9800 2 40 ~ 0
BANK2F3M13
Text Label 16000 6250 2 40 ~ 0 Text Label 16000 6250 2 40 ~ 0
BANK2F3M12 BANK2F3M12
Text Label 11850 9600 2 40 ~ 0 Text Label 11850 9600 2 40 ~ 0
@ -673,21 +667,6 @@ F 6 "RES 39 OHM 1/16W 5% 0402 SMD" H 11200 10000 60 0001 C CNN "Description"
0 -1 -1 0 0 -1 -1 0
$EndComp $EndComp
$Comp $Comp
L R R97
U 1 1 503F98AA
P 11200 9800
F 0 "R97" V 11280 9800 50 0000 C CNN
F 1 "39" V 11200 9800 50 0000 C CNN
F 2 "" H 11200 9800 60 0001 C CNN
F 3 "" H 11200 9800 60 0001 C CNN
F 4 "Stackpole" H 11200 9800 60 0001 C CNN "Manufacturer"
F 5 "RMCF0402JT39R0" H 11200 9800 60 0001 C CNN "Part Number"
F 6 "RES 39 OHM 1/16W 5% 0402 SMD" H 11200 9800 60 0001 C CNN "Description"
F 7 "DNP" V 11250 10050 60 0000 C CNN "Note"
1 11200 9800
0 -1 -1 0
$EndComp
$Comp
L R R96 L R R96
U 1 1 503F989E U 1 1 503F989E
P 11200 9600 P 11200 9600
@ -2519,8 +2498,6 @@ Text Label 10650 9400 0 40 ~ 0
SGPIO11 SGPIO11
Text Label 10650 9600 0 40 ~ 0 Text Label 10650 9600 0 40 ~ 0
SGPIO12 SGPIO12
Text Label 10650 9800 0 40 ~ 0
SGPIO8
Text Label 10650 10000 0 40 ~ 0 Text Label 10650 10000 0 40 ~ 0
SGPIO4 SGPIO4
Text Label 10650 10200 0 40 ~ 0 Text Label 10650 10200 0 40 ~ 0
@ -3564,14 +3541,10 @@ Wire Wire Line
11450 9600 11850 9600 11450 9600 11850 9600
Wire Wire Line Wire Wire Line
10650 9400 10950 9400 10650 9400 10950 9400
Wire Wire Line
10650 9800 10950 9800
Wire Wire Line Wire Wire Line
10650 10200 10950 10200 10650 10200 10950 10200
Wire Wire Line Wire Wire Line
11450 10400 11850 10400 11450 10400 11850 10400
Wire Wire Line
11450 9800 11850 9800
Wire Wire Line Wire Wire Line
11450 10200 11850 10200 11450 10200 11850 10200
Wire Wire Line Wire Wire Line
@ -4145,8 +4118,6 @@ Wire Wire Line
14100 8950 14100 9050 14100 8950 14100 9050
Wire Wire Line Wire Wire Line
15600 6850 16000 6850 15600 6850 16000 6850
Wire Wire Line
15600 6450 16000 6450
Wire Wire Line Wire Wire Line
15600 6250 16000 6250 15600 6250 16000 6250
Wire Wire Line Wire Wire Line
@ -4535,4 +4506,5 @@ Wire Wire Line
1600 3150 1600 3350 1600 3150 1600 3350
Connection ~ 1600 3350 Connection ~ 1600 3350
NoConn ~ 11600 7850 NoConn ~ 11600 7850
NoConn ~ 15600 6450
$EndSCHEMATC $EndSCHEMATC