diff --git a/firmware/sgpio_passthrough_rom_to_ram/Makefile b/firmware/sgpio_passthrough_rom_to_ram/Makefile new file mode 100644 index 00000000..98eb5746 --- /dev/null +++ b/firmware/sgpio_passthrough_rom_to_ram/Makefile @@ -0,0 +1,10 @@ +# Hey Emacs, this is a -*- makefile -*- + +BINARY = sgpio_passthrough + +SRC = $(BINARY).c \ + ../common/hackrf_core.c \ + ../common/si5351c.c + +LDSCRIPT = ../common/LPC4330_M4_rom_to_ram.ld +include ../common/Makefile_inc.mk diff --git a/firmware/sgpio_passthrough_rom_to_ram/README b/firmware/sgpio_passthrough_rom_to_ram/README new file mode 100644 index 00000000..2489f791 --- /dev/null +++ b/firmware/sgpio_passthrough_rom_to_ram/README @@ -0,0 +1,5 @@ +A program to test SGPIO with CPLD passthrough Input & Output via the SGPIO CPLD interface (P8 BANK2_AUX). +For this test connect P10 BANK1_AUX AUX9 pin to +1V8 (in order to have P8 BANK2_AUX AUX1 to 16 as Output). +This test requires: + * JellyBean+Lemondrop(to set clock at 204MHz). + * CPLD X2C64A hardware\jellybean\sgpio_if_passthrough\sgpio_if_passthrough.svf to be loaded first. diff --git a/firmware/sgpio_passthrough_rom_to_ram/Test_SGPIO0_to15.ods b/firmware/sgpio_passthrough_rom_to_ram/Test_SGPIO0_to15.ods new file mode 100644 index 00000000..a3843c9e Binary files /dev/null and b/firmware/sgpio_passthrough_rom_to_ram/Test_SGPIO0_to15.ods differ diff --git a/firmware/sgpio_passthrough_rom_to_ram/Test_SGPIO0_to15.pdf b/firmware/sgpio_passthrough_rom_to_ram/Test_SGPIO0_to15.pdf new file mode 100644 index 00000000..0ecf83d4 Binary files /dev/null and b/firmware/sgpio_passthrough_rom_to_ram/Test_SGPIO0_to15.pdf differ diff --git a/firmware/sgpio_passthrough_rom_to_ram/Test_SGPIO_GPIO_mode_test_sgpio_interface.txt b/firmware/sgpio_passthrough_rom_to_ram/Test_SGPIO_GPIO_mode_test_sgpio_interface.txt new file mode 100644 index 00000000..6c2f3ba9 --- /dev/null +++ b/firmware/sgpio_passthrough_rom_to_ram/Test_SGPIO_GPIO_mode_test_sgpio_interface.txt @@ -0,0 +1,68 @@ + +Test SGPIO GPIO mode, with LPC4330@204MHz (JellyBean+Lemondrop) and code executed in RAM. + +Test1: +------ +while(1) +{ + for (uint_fast8_t i = 0; i < 8; i++) + { + SGPIO_GPIO_OUTREG ^= (1L << i); + + } +} +Oscilloscope result (on SGPIO0): Frequency 750KHz => 272 cycles + +Test2: +------ +while(1) +{ + __asm__(" nop"); + __asm__(" nop"); + __asm__(" nop"); + __asm__(" nop"); + __asm__(" nop"); + __asm__(" nop"); + __asm__(" nop"); + __asm__(" nop"); + __asm__(" nop"); + __asm__(" nop"); + __asm__(" nop"); + __asm__(" nop"); + SGPIO_GPIO_OUTREG ^= 0x5555; +} +Oscilloscope result (on SGPIO0): 3.923 MHz => 52 cycles + +Test3: +------ +while(1) +{ + SGPIO_GPIO_OUTREG ^= 0x5555; +} +Oscilloscope result (on SGPIO0): Frequency 7.28MHz => 28 cycles + +Test4: +------ +while(1) +{ + __asm__(" nop"); + __asm__(" nop"); + __asm__(" nop"); + __asm__(" nop"); + SGPIO_GPIO_OUTREG = 0x5555; + __asm__(" nop"); + __asm__(" nop"); + __asm__(" nop"); + __asm__(" nop"); + SGPIO_GPIO_OUTREG = 0xAAAA; +} +Oscilloscope result (on SGPIO0): Frequency 17MHz => 12 cycles + +Test5: +------ +while(1) +{ + SGPIO_GPIO_OUTREG = 0x5555; + SGPIO_GPIO_OUTREG = 0xAAAA; +} +Oscilloscope result (on SGPIO0): Frequency 25.5MHz => 8 cycles diff --git a/firmware/sgpio_passthrough_rom_to_ram/sgpio_passthrough.c b/firmware/sgpio_passthrough_rom_to_ram/sgpio_passthrough.c new file mode 100644 index 00000000..c5525c57 --- /dev/null +++ b/firmware/sgpio_passthrough_rom_to_ram/sgpio_passthrough.c @@ -0,0 +1,419 @@ +/* + * Copyright 2012 Michael Ossmann + * Copyright (C) 2012 Jared Boone + * Copyright (C) 2012 Benjamin Vernoux + * + * This file is part of HackRF. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 51 Franklin Street, + * Boston, MA 02110-1301, USA. + */ + +#include +#include +#include +#include +#include + +#include + +void pin_setup(void) { + /* Configure SCU Pin Mux as GPIO */ + scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_LED3, SCU_GPIO_FAST); + + scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_FAST); + + /* Configure all GPIO as Input (safe state) */GPIO0_DIR = 0; + GPIO1_DIR = 0; + GPIO2_DIR = 0; + GPIO3_DIR = 0; + GPIO4_DIR = 0; + GPIO5_DIR = 0; + GPIO6_DIR = 0; + GPIO7_DIR = 0; + + /* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */ + GPIO2_DIR |= (PIN_LED1 | PIN_LED2 | PIN_LED3); + + /* GPIO3[6] on P6_10 as output. */ + GPIO3_DIR |= PIN_EN1V8; + + /* Configure SSP1 Peripheral (to be moved later in SSP driver) */ + scu_pinmux(SCU_SSP1_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5)); + scu_pinmux(SCU_SSP1_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5)); + scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1)); + scu_pinmux(SCU_SSP1_SSEL, (SCU_SSP_IO | SCU_CONF_FUNCTION1)); +} + +void enable_1v8_power() { + gpio_set(PORT_EN1V8, PIN_EN1V8); +} + +void release_cpld_jtag_pins() { + scu_pinmux(SCU_PINMUX_CPLD_TDO, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION4); + scu_pinmux(SCU_PINMUX_CPLD_TCK, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0); + scu_pinmux(SCU_PINMUX_CPLD_TMS, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0); + scu_pinmux(SCU_PINMUX_CPLD_TDI, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0); + + GPIO_DIR(PORT_CPLD_TDO) &= ~PIN_CPLD_TDO; + GPIO_DIR(PORT_CPLD_TCK) &= ~PIN_CPLD_TCK; + GPIO_DIR(PORT_CPLD_TMS) &= ~PIN_CPLD_TMS; + GPIO_DIR(PORT_CPLD_TDI) &= ~PIN_CPLD_TDI; +} + +void configure_sgpio_pin_functions() { + scu_pinmux(SCU_PINMUX_SGPIO0, SCU_GPIO_FAST | SCU_CONF_FUNCTION3); + scu_pinmux(SCU_PINMUX_SGPIO1, SCU_GPIO_FAST | SCU_CONF_FUNCTION3); + scu_pinmux(SCU_PINMUX_SGPIO2, SCU_GPIO_FAST | SCU_CONF_FUNCTION2); + scu_pinmux(SCU_PINMUX_SGPIO3, SCU_GPIO_FAST | SCU_CONF_FUNCTION2); + scu_pinmux(SCU_PINMUX_SGPIO4, SCU_GPIO_FAST | SCU_CONF_FUNCTION2); + scu_pinmux(SCU_PINMUX_SGPIO5, SCU_GPIO_FAST | SCU_CONF_FUNCTION2); + scu_pinmux(SCU_PINMUX_SGPIO6, SCU_GPIO_FAST | SCU_CONF_FUNCTION0); + scu_pinmux(SCU_PINMUX_SGPIO7, SCU_GPIO_FAST | SCU_CONF_FUNCTION6); + scu_pinmux(SCU_PINMUX_SGPIO8, SCU_GPIO_FAST | SCU_CONF_FUNCTION6); + scu_pinmux(SCU_PINMUX_SGPIO9, SCU_GPIO_FAST | SCU_CONF_FUNCTION7); + scu_pinmux(SCU_PINMUX_SGPIO10, SCU_GPIO_FAST | SCU_CONF_FUNCTION6); + scu_pinmux(SCU_PINMUX_SGPIO11, SCU_GPIO_FAST | SCU_CONF_FUNCTION6); + scu_pinmux(SCU_PINMUX_SGPIO12, SCU_GPIO_FAST | SCU_CONF_FUNCTION6); + scu_pinmux(SCU_PINMUX_SGPIO13, SCU_GPIO_FAST | SCU_CONF_FUNCTION7); + scu_pinmux(SCU_PINMUX_SGPIO14, SCU_GPIO_FAST | SCU_CONF_FUNCTION7); + scu_pinmux(SCU_PINMUX_SGPIO15, SCU_GPIO_FAST | SCU_CONF_FUNCTION7); +} + +void test_sgpio_sliceA_D(void) +{ + SGPIO_GPIO_OENREG = 0; // All inputs for the moment. + + // Disable all counters during configuration + SGPIO_CTRL_ENABLE = 0; + + // Configure pin functions. + configure_sgpio_pin_functions(); + + /****************************************************/ + /* Enable SGPIO pin outputs. */ + /****************************************************/ + SGPIO_GPIO_OENREG = + 0xFFFF; // data: output for SGPIO0 to SGPIO15 + + /*******************************************************************************/ + /* SGPIO pin 0 outputs slice A bit 0. (see Table 212. Output pin multiplexing) */ + /*******************************************************************************/ + SGPIO_OUT_MUX_CFG(0) = + (0L << 4) | // P_OE_CFG = X + (0L << 0); // P_OUT_CFG = 0, dout_doutm1 (1-bit mode) + + // SGPIO pin 12 outputs slice D bit 0. (see Table 212. Output pin multiplexing) + SGPIO_OUT_MUX_CFG(12) = + (0L << 4) | // P_OE_CFG = X + (0L << 0); // P_OUT_CFG = 0, dout_doutm1 (1-bit mode) + + /****************************************************/ + /* Slice A */ + /****************************************************/ + SGPIO_MUX_CFG(SGPIO_SLICE_A) = + (0L << 12) | // CONCAT_ORDER = 0 (self-loop) + (1L << 11) | // CONCAT_ENABLE = 1 (concatenate data) + (0L << 9) | // QUALIFIER_SLICE_MODE = X + (0L << 7) | // QUALIFIER_PIN_MODE = X + (0L << 5) | // QUALIFIER_MODE = 0 (enable) + (0L << 3) | // CLK_SOURCE_SLICE_MODE = 0, slice D + (0L << 1) | // CLK_SOURCE_PIN_MODE = X + (0L << 0); // EXT_CLK_ENABLE = 0, internal clock signal (slice) + + SGPIO_SLICE_MUX_CFG(SGPIO_SLICE_A) = + (0L << 8) | // INV_QUALIFIER = 0 (use normal qualifier) + (0L << 6) | // PARALLEL_MODE = 0 (shift 1 bit per clock) + (0L << 4) | // DATA_CAPTURE_MODE = 0 (detect rising edge) + (0L << 3) | // INV_OUT_CLK = 0 (normal clock) + (0L << 2) | // CLKGEN_MODE = 0 (use clock from COUNTER) + (0L << 1) | // CLK_CAPTURE_MODE = 0 (use rising clock edge) + (0L << 0); // MATCH_MODE = 0 (do not match data) + + SGPIO_PRESET(SGPIO_SLICE_A) = 1; + SGPIO_COUNT(SGPIO_SLICE_A) = 0; + SGPIO_POS(SGPIO_SLICE_A) = (0x1FL << 8) | (0x1FL << 0); + SGPIO_REG(SGPIO_SLICE_A) = 0xAAAAAAAA; // Primary output data register + SGPIO_REG_SS(SGPIO_SLICE_A) = 0xAAAAAAAA; // Shadow output data register + + /****************************************************/ + /* Slice D (clock for Slice A) */ + /****************************************************/ + SGPIO_MUX_CFG(SGPIO_SLICE_D) = + (0L << 12) | // CONCAT_ORDER = 0 (self-loop) + (1L << 11) | // CONCAT_ENABLE = 1 (concatenate data) + (0L << 9) | // QUALIFIER_SLICE_MODE = X + (0L << 7) | // QUALIFIER_PIN_MODE = X + (0L << 5) | // QUALIFIER_MODE = 0 (enable) + (0L << 3) | // CLK_SOURCE_SLICE_MODE = 0, slice D + (0L << 1) | // CLK_SOURCE_PIN_MODE = X + (0L << 0); // EXT_CLK_ENABLE = 0, internal clock signal (slice) + + SGPIO_SLICE_MUX_CFG(SGPIO_SLICE_D) = + (0L << 8) | // INV_QUALIFIER = 0 (use normal qualifier) + (0L << 6) | // PARALLEL_MODE = 0 (shift 1 bit per clock) + (0L << 4) | // DATA_CAPTURE_MODE = 0 (detect rising edge) + (0L << 3) | // INV_OUT_CLK = 0 (normal clock) + (0L << 2) | // CLKGEN_MODE = 0 (use clock from COUNTER) + (0L << 1) | // CLK_CAPTURE_MODE = 0 (use rising clock edge) + (0L << 0); // MATCH_MODE = 0 (do not match data) + + SGPIO_PRESET(SGPIO_SLICE_D) = 0; + SGPIO_COUNT(SGPIO_SLICE_D) = 0; + SGPIO_POS(SGPIO_SLICE_D) = (0x1FL << 8) | (0x1FL << 0); + SGPIO_REG(SGPIO_SLICE_D) = 0xAAAAAAAA; // Primary output data register + SGPIO_REG_SS(SGPIO_SLICE_D) = 0xAAAAAAAA; // Shadow output data register + + + /****************************************************/ + /* Start SGPIO operation by enabling slice clocks. */ + /****************************************************/ + SGPIO_CTRL_ENABLE = + (1L << SGPIO_SLICE_D) | // Slice D + (1L << SGPIO_SLICE_A); // Slice A + // Start SGPIO operation by enabling slice clocks. + + /* + Expected: + SGPIO12 = MCU Freq/2 + SGPIO0 = SGPIO12/2 MHz= 51MHz (SliceD/2) + */ + +} + + +/*******************************************************************************/ +/* Output 1bit table (see Table 212. Output pin multiplexing) */ +/* SGPIO pin 00 outputs slice A bit 0. */ +/* SGPIO pin 01 outputs slice I bit 0. */ +/* SGPIO pin 02 outputs slice E bit 0. */ +/* SGPIO pin 03 outputs slice J bit 0. */ +/* SGPIO pin 04 outputs slice C bit 0. */ +/* SGPIO pin 05 outputs slice K bit 0. */ +/* SGPIO pin 06 outputs slice F bit 0. */ +/* SGPIO pin 07 outputs slice L bit 0. */ +/* SGPIO pin 08 outputs slice B bit 0. */ +/* SGPIO pin 09 outputs slice M bit 0. */ +/* SGPIO pin 10 outputs slice G bit 0. */ +/* SGPIO pin 11 outputs slice N bit 0. */ +/* SGPIO pin 12 outputs slice D bit 0. */ +/* SGPIO pin 13 outputs slice O bit 0. */ +/* SGPIO pin 14 outputs slice H bit 0. */ +/* SGPIO pin 15 outputs slice P bit 0. */ +/*******************************************************************************/ +const u8 slice_preset_tab[16] = +{ + 0, /* Idx00 = Slice A => SGPIO0 Freq Div by 1=0 */ + 8, /* Idx01 = Slice B => SGPIO8 Freq Div by 9=8 */ + 4, /* Idx02 = Slice C => SGPIO4 Freq Div by 5=4 */ + 12, /* Idx03 = Slice D => SGPIO12 Freq Div by 13=12 */ + 2, /* Idx04 = Slice E => SGPIO2 Freq Div by 3=2 */ + 6, /* Idx05 = Slice F => SGPIO6 Freq Div by 7=6 */ + 10, /* Idx06 = Slice G => SGPIO10 Freq Div by 11=10 */ + 14, /* Idx07 = Slice H => SGPIO14 Freq Div by 15=14 */ + 1, /* Idx08 = Slice I => SGPIO1 Freq Div by 2=1 */ + 3, /* Idx09 = Slice J => SGPIO3 Freq Div by 4=3 */ + 5, /* Idx10 = Slice K => SGPIO5 Freq Div by 6=5 */ + 7, /* Idx11 = Slice L => SGPIO7 Freq Div by 8=7 */ + 9, /* Idx12 = Slice M => SGPIO9 Freq Div by 10=9 */ + 11, /* Idx13 = Slice N => SGPIO11 Freq Div by 12=11 */ + 13, /* Idx14 = Slice O => SGPIO13 Freq Div by 14=13 */ + 15 /* Idx15 = Slice P => SGPIO15 Freq Div by 16=15 */ +}; + +void test_sgpio_all_slices(void) +{ + + SGPIO_GPIO_OENREG = 0; // All inputs for the moment. + + // Disable all counters during configuration + SGPIO_CTRL_ENABLE = 0; + + // Configure pin functions. + configure_sgpio_pin_functions(); + + /****************************************************/ + /* Enable SGPIO pin outputs. */ + /****************************************************/ + SGPIO_GPIO_OENREG = + 0xFFFF; // data: output for SGPIO0 to SGPIO15 + + for(uint_fast8_t i=0; i<16; i++) + { + SGPIO_OUT_MUX_CFG(i) = + (0L << 4) | // P_OE_CFG = X + (0L << 0); // P_OUT_CFG = 0, dout_doutm1 (1-bit mode) + } + + /****************************************************/ + /* Slice A to P */ + /****************************************************/ + for(uint_fast8_t i=0; i<16; i++) + { + SGPIO_MUX_CFG(i) = + (0L << 12) | // CONCAT_ORDER = 0 (self-loop) + (1L << 11) | // CONCAT_ENABLE = 1 (concatenate data) + (0L << 9) | // QUALIFIER_SLICE_MODE = X + (0L << 7) | // QUALIFIER_PIN_MODE = X + (0L << 5) | // QUALIFIER_MODE = 0 (enable) + (0L << 3) | // CLK_SOURCE_SLICE_MODE = 0, slice D + (0L << 1) | // CLK_SOURCE_PIN_MODE = X + (0L << 0); // EXT_CLK_ENABLE = 0, internal clock signal (slice) + + SGPIO_SLICE_MUX_CFG(i) = + (0L << 8) | // INV_QUALIFIER = 0 (use normal qualifier) + (0L << 6) | // PARALLEL_MODE = 0 (shift 1 bit per clock) + (0L << 4) | // DATA_CAPTURE_MODE = 0 (detect rising edge) + (0L << 3) | // INV_OUT_CLK = 0 (normal clock) + (0L << 2) | // CLKGEN_MODE = 0 (use clock from COUNTER) + (0L << 1) | // CLK_CAPTURE_MODE = 0 (use rising clock edge) + (0L << 0); // MATCH_MODE = 0 (do not match data) + + SGPIO_PRESET(i) = slice_preset_tab[i]; + SGPIO_COUNT(i) = 0; + SGPIO_POS(i) = (0x1FL << 8) | (0x1FL << 0); + SGPIO_REG(i) = 0xAAAAAAAA; // Primary output data register + SGPIO_REG_SS(i) = 0xAAAAAAAA; // Shadow output data register + } + + /****************************************************/ + /* Start SGPIO operation by enabling slice clocks. */ + /****************************************************/ + SGPIO_CTRL_ENABLE = 0xFFFF; /* Start all slices A to P */ +/* + (1L << SGPIO_SLICE_D) | // Slice D + (1L << SGPIO_SLICE_A); // Slice A + // Start SGPIO operation by enabling slice clocks. +*/ + /* + Expected: + MCU Freq MHz = 204 + SGPIO Theorical Freq MHz + SGPIO00 = 102,00000 + SGPIO01 = 51,00000 + SGPIO02 = 34,00000 + SGPIO03 = 25,50000 + SGPIO04 = 20,40000 + SGPIO05 = 17,00000 + SGPIO06 = 14,57143 + SGPIO07 = 12,75000 + SGPIO08 = 11,33333 + SGPIO09 = 10,20000 + SGPIO10 = 9,27273 + SGPIO11 = 8,50000 + SGPIO12 = 7,84615 + SGPIO13 = 7,28571 + SGPIO14 = 6,80000 + SGPIO15 = 6,37500 + TitanMKD: I have problems with my boards and this test see document Test_SGPIO0_to15.ods / Test_SGPIO0_to15.pdf + */ +} + +void test_sgpio_interface(void) +{ + SGPIO_GPIO_OENREG = 0; // All inputs for the moment. + + // Disable all counters during configuration + SGPIO_CTRL_ENABLE = 0; + + configure_sgpio_pin_functions(); + + // Make all SGPIO controlled by SGPIO's "GPIO" registers + for (uint_fast8_t i = 0; i < 16; i++) { + SGPIO_OUT_MUX_CFG(i) = (0L << 4) | (4L << 0); + } + + // Enable SGPIO pin outputs (SGPIO0 to 15). + SGPIO_GPIO_OENREG = 0xFFFF; + + /* Set values for SGPIO0 to 15 */ + while (1) + { + // 750KHz => 272 cycles + /* + for (uint_fast8_t i = 0; i < 8; i++) { + SGPIO_GPIO_OUTREG ^= (1L << i); + + } + */ + + // 3.923 MHz => 52 cycles + __asm__(" nop"); + __asm__(" nop"); + __asm__(" nop"); + __asm__(" nop"); + __asm__(" nop"); + __asm__(" nop"); + __asm__(" nop"); + __asm__(" nop"); + __asm__(" nop"); + __asm__(" nop"); + __asm__(" nop"); + __asm__(" nop"); + SGPIO_GPIO_OUTREG ^= 0x5555; + + // 7.28 MHz => 28 cycles + /* + SGPIO_GPIO_OUTREG ^= 0x5555; + */ + + // 17 MHz => 12 cycles + /* + __asm__(" nop"); + __asm__(" nop"); + __asm__(" nop"); + __asm__(" nop"); + SGPIO_GPIO_OUTREG = 0x5555; + __asm__(" nop"); + __asm__(" nop"); + __asm__(" nop"); + __asm__(" nop"); + SGPIO_GPIO_OUTREG = 0xAAAA; + */ + // 25.50 MHz => 8 cycles + /* + SGPIO_GPIO_OUTREG = 0x5555; + SGPIO_GPIO_OUTREG = 0xAAAA; + */ + } + + /* TitanMKD: I have problems with my board with this test (see test_sgpio_all_slices()) */ +} + +int main(void) +{ + pin_setup(); + enable_1v8_power(); + cpu_clock_init(); + ssp1_init(); + + CGU_BASE_PERIPH_CLK = (CGU_BASE_CLK_AUTOBLOCK + | (CGU_SRC_PLL1 << CGU_BASE_CLK_SEL_SHIFT)); + + CGU_BASE_APB1_CLK = (CGU_BASE_CLK_AUTOBLOCK + | (CGU_SRC_PLL1 << CGU_BASE_CLK_SEL_SHIFT)); + + gpio_set(PORT_LED1_3, PIN_LED1); + + //test_sgpio_sliceA_D(); + test_sgpio_interface(); + //test_sgpio_all_slices(); + + while(1); + + return 0; +} diff --git a/hardware/jellybean/JellyBean_pins.png b/hardware/jellybean/JellyBean_pins.png new file mode 100644 index 00000000..615af19f Binary files /dev/null and b/hardware/jellybean/JellyBean_pins.png differ diff --git a/hardware/jellybean/jellybean_board_PCB_layers.pdf b/hardware/jellybean/jellybean_board_PCB_layers.pdf new file mode 100644 index 00000000..7d0f14f3 Binary files /dev/null and b/hardware/jellybean/jellybean_board_PCB_layers.pdf differ diff --git a/hardware/jellybean/jellybean_schematic.pdf b/hardware/jellybean/jellybean_schematic.pdf new file mode 100644 index 00000000..2e8ea771 Binary files /dev/null and b/hardware/jellybean/jellybean_schematic.pdf differ diff --git a/hardware/jellybean/sgpio_if_passthrough/README.md b/hardware/jellybean/sgpio_if_passthrough/README.md new file mode 100644 index 00000000..2fc7a383 --- /dev/null +++ b/hardware/jellybean/sgpio_if_passthrough/README.md @@ -0,0 +1,33 @@ + +CPLD interface to expose LPC43xx microcontroller SGPIO peripheral, either +as all inputs or all outputs. + +Requirements +============ + +To build this VHDL project and produce an SVF file for flashing the CPLD: + +* Xilinx WebPACK 13.4 for Windows or Linux. + +* BSDL model files for Xilinx CoolRunner-II XC264A, available at xilinx.com, + in the "Device Models" Support Resources section of the CoolRunner-II + Product Support & Documentation page. Only one file from the BSDL package is + required, and the "program" script below expects it to be at the relative + path "bsdl/xc2c/xc2c64.bsd". + +To program the SVF file into the CPLD: + +* Dangerous Prototypes Bus Blaster v2: + * Configured with JTAGKey buffers. + * Connected to CPLD JTAG signals on Jellybean. + +* urJTAG built with libftdi support. + +To Program +========== + +./program + +...which connects to the Bus Blaster interface 0, sets the BSDL directory, +detects devices on the JTAG chain, and writes the sgpio_if_passthrough.svf +file to the CPLD. diff --git a/hardware/jellybean/sgpio_if_passthrough/program b/hardware/jellybean/sgpio_if_passthrough/program new file mode 100755 index 00000000..0aba6b0e --- /dev/null +++ b/hardware/jellybean/sgpio_if_passthrough/program @@ -0,0 +1,10 @@ +#!/bin/sh + +echo Program Xilinx CoolRunner-II CPLD on Jellybean, using Bus Blaster v2 + +jtag < + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hardware/jellybean/sgpio_if_passthrough/top.ucf b/hardware/jellybean/sgpio_if_passthrough/top.ucf new file mode 100755 index 00000000..cd6a2e70 --- /dev/null +++ b/hardware/jellybean/sgpio_if_passthrough/top.ucf @@ -0,0 +1,89 @@ +# +# Copyright 2012 Jared Boone +# +# This file is part of HackRF. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. + +NET "CODEC_CLK" LOC="23" |FAST |IOSTANDARD=LVCMOS18; +NET "CODEC_X2_CLK" LOC="27" |FAST |IOSTANDARD=LVCMOS18; +#NET "GCLK0" LOC="22" |FAST |IOSTANDARD=LVCMOS18; + +NET "CODEC_X2_CLK" TNM_NET = CODEC_X2_CLK; +TIMESPEC TS_codec_x2_data = PERIOD "CODEC_X2_CLK" 50 ns; + +NET "DA<7>" LOC="35" |FAST |IOSTANDARD=LVCMOS18; +NET "DA<6>" LOC="36" |FAST |IOSTANDARD=LVCMOS18; +NET "DA<5>" LOC="37" |FAST |IOSTANDARD=LVCMOS18; +NET "DA<4>" LOC="39" |FAST |IOSTANDARD=LVCMOS18; +NET "DA<3>" LOC="40" |FAST |IOSTANDARD=LVCMOS18; +NET "DA<2>" LOC="41" |FAST |IOSTANDARD=LVCMOS18; +NET "DA<1>" LOC="42" |FAST |IOSTANDARD=LVCMOS18; +NET "DA<0>" LOC="43" |FAST |IOSTANDARD=LVCMOS18; + +NET "DD<9>" LOC="17" |FAST |IOSTANDARD=LVCMOS18; +NET "DD<8>" LOC="18" |FAST |IOSTANDARD=LVCMOS18; +NET "DD<7>" LOC="19" |FAST |IOSTANDARD=LVCMOS18; +NET "DD<6>" LOC="24" |FAST |IOSTANDARD=LVCMOS18; +NET "DD<5>" LOC="28" |FAST |IOSTANDARD=LVCMOS18; +NET "DD<4>" LOC="29" |FAST |IOSTANDARD=LVCMOS18; +NET "DD<3>" LOC="30" |FAST |IOSTANDARD=LVCMOS18; +NET "DD<2>" LOC="32" |FAST |IOSTANDARD=LVCMOS18; +NET "DD<1>" LOC="33" |FAST |IOSTANDARD=LVCMOS18; +NET "DD<0>" LOC="34" |FAST |IOSTANDARD=LVCMOS18; + +NET "B1AUX<16>" LOC="60" |FAST |IOSTANDARD=LVCMOS18; +NET "B1AUX<15>" LOC="58" |FAST |IOSTANDARD=LVCMOS18; +NET "B1AUX<14>" LOC="56" |FAST |IOSTANDARD=LVCMOS18; +NET "B1AUX<13>" LOC="55" |FAST |IOSTANDARD=LVCMOS18; +NET "B1AUX<12>" LOC="53" |FAST |IOSTANDARD=LVCMOS18; +NET "B1AUX<11>" LOC="52" |FAST |IOSTANDARD=LVCMOS18; +NET "B1AUX<10>" LOC="50" |FAST |IOSTANDARD=LVCMOS18; +NET "B1AUX<9>" LOC="49" |FAST |IOSTANDARD=LVCMOS18; + +NET "SGPIO<15>" LOC="78" |FAST |IOSTANDARD=LVCMOS33; +NET "SGPIO<14>" LOC="81" |FAST |IOSTANDARD=LVCMOS33; +NET "SGPIO<13>" LOC="90" |FAST |IOSTANDARD=LVCMOS33; +NET "SGPIO<12>" LOC="70" |FAST |IOSTANDARD=LVCMOS33; +NET "SGPIO<11>" LOC="71" |FAST |IOSTANDARD=LVCMOS33; +NET "SGPIO<10>" LOC="76" |FAST |IOSTANDARD=LVCMOS33; +NET "SGPIO<9>" LOC="91" |FAST |IOSTANDARD=LVCMOS33; +NET "SGPIO<8>" LOC="68" |FAST |IOSTANDARD=LVCMOS33; +NET "SGPIO<7>" LOC="77" |FAST |IOSTANDARD=LVCMOS33; +NET "SGPIO<6>" LOC="61" |FAST |IOSTANDARD=LVCMOS33; +NET "SGPIO<5>" LOC="64" |FAST |IOSTANDARD=LVCMOS33; +NET "SGPIO<4>" LOC="67" |FAST |IOSTANDARD=LVCMOS33; +NET "SGPIO<3>" LOC="72" |FAST |IOSTANDARD=LVCMOS33; +NET "SGPIO<2>" LOC="74" |FAST |IOSTANDARD=LVCMOS33; +NET "SGPIO<1>" LOC="79" |FAST |IOSTANDARD=LVCMOS33; +NET "SGPIO<0>" LOC="89" |FAST |IOSTANDARD=LVCMOS33; + +NET "B2AUX<16>" LOC="92" |FAST |IOSTANDARD=LVCMOS33; +NET "B2AUX<15>" LOC="94" |FAST |IOSTANDARD=LVCMOS33; +NET "B2AUX<14>" LOC="97" |FAST |IOSTANDARD=LVCMOS33; +NET "B2AUX<13>" LOC="99" |FAST |IOSTANDARD=LVCMOS33; +NET "B2AUX<12>" LOC="1" |FAST |IOSTANDARD=LVCMOS33; +NET "B2AUX<11>" LOC="2" |FAST |IOSTANDARD=LVCMOS33; +NET "B2AUX<10>" LOC="3" |FAST |IOSTANDARD=LVCMOS33; +NET "B2AUX<9>" LOC="4" |FAST |IOSTANDARD=LVCMOS33; +NET "B2AUX<8>" LOC="6" |FAST |IOSTANDARD=LVCMOS33; +NET "B2AUX<7>" LOC="7" |FAST |IOSTANDARD=LVCMOS33; +NET "B2AUX<6>" LOC="8" |FAST |IOSTANDARD=LVCMOS33; +NET "B2AUX<5>" LOC="9" |FAST |IOSTANDARD=LVCMOS33; +NET "B2AUX<4>" LOC="10" |FAST |IOSTANDARD=LVCMOS33; +NET "B2AUX<3>" LOC="11" |FAST |IOSTANDARD=LVCMOS33; +NET "B2AUX<2>" LOC="12" |FAST |IOSTANDARD=LVCMOS33; +NET "B2AUX<1>" LOC="13" |FAST |IOSTANDARD=LVCMOS33; diff --git a/hardware/jellybean/sgpio_if_passthrough/top.vhd b/hardware/jellybean/sgpio_if_passthrough/top.vhd new file mode 100755 index 00000000..55be76b6 --- /dev/null +++ b/hardware/jellybean/sgpio_if_passthrough/top.vhd @@ -0,0 +1,60 @@ +-- +-- Copyright 2012 Jared Boone +-- +-- This file is part of HackRF. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; see the file COPYING. If not, write to +-- the Free Software Foundation, Inc., 51 Franklin Street, +-- Boston, MA 02110-1301, USA. + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +library UNISIM; +use UNISIM.vcomponents.all; + +entity top is + Port( + SGPIO : inout std_logic_vector(15 downto 0); + + DA : in std_logic_vector(7 downto 0); + DD : out std_logic_vector(9 downto 0); + + CODEC_CLK : in std_logic; + CODEC_X2_CLK : in std_logic; + + B1AUX : in std_logic_vector(16 downto 9); + B2AUX : inout std_logic_vector(16 downto 1) + ); + +end top; + +architecture Behavioral of top is + type transfer_direction is (to_sgpio, from_sgpio); + signal transfer_direction_i : transfer_direction; + +begin + + transfer_direction_i <= to_sgpio when B1AUX(9) = '0' + else from_sgpio; + + DD <= (DD'high => '1', others => '0'); + + B2AUX <= SGPIO when transfer_direction_i = from_sgpio + else (others => 'Z'); + + SGPIO <= B2AUX when transfer_direction_i = to_sgpio + else (others => 'Z'); + +end Behavioral;