diff --git a/firmware/common/hackrf_core.c b/firmware/common/hackrf_core.c
index 88accc11..2f99d7fd 100644
--- a/firmware/common/hackrf_core.c
+++ b/firmware/common/hackrf_core.c
@@ -254,3 +254,54 @@ void ssp1_set_mode_max5864(void)
 		SSP_MASTER,
 		SSP_SLAVE_OUT_ENABLE);
 }
+
+void pin_setup(void) {
+	/* Release CPLD JTAG pins */
+	scu_pinmux(SCU_PINMUX_CPLD_TDO, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION4);
+	scu_pinmux(SCU_PINMUX_CPLD_TCK, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
+	scu_pinmux(SCU_PINMUX_CPLD_TMS, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
+	scu_pinmux(SCU_PINMUX_CPLD_TDI, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
+	
+	GPIO_DIR(PORT_CPLD_TDO) &= ~PIN_CPLD_TDO;
+	GPIO_DIR(PORT_CPLD_TCK) &= ~PIN_CPLD_TCK;
+	GPIO_DIR(PORT_CPLD_TMS) &= ~PIN_CPLD_TMS;
+	GPIO_DIR(PORT_CPLD_TDI) &= ~PIN_CPLD_TDI;
+	
+	/* Configure SCU Pin Mux as GPIO */
+	scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_FAST);
+	scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_FAST);
+	scu_pinmux(SCU_PINMUX_LED3, SCU_GPIO_FAST);
+	
+	scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_FAST);
+	
+	scu_pinmux(SCU_PINMUX_BOOT0, SCU_GPIO_FAST);
+	scu_pinmux(SCU_PINMUX_BOOT1, SCU_GPIO_FAST);
+	scu_pinmux(SCU_PINMUX_BOOT2, SCU_GPIO_FAST);
+	scu_pinmux(SCU_PINMUX_BOOT3, SCU_GPIO_FAST);
+	
+	/* Configure all GPIO as Input (safe state) */
+	GPIO0_DIR = 0;
+	GPIO1_DIR = 0;
+	GPIO2_DIR = 0;
+	GPIO3_DIR = 0;
+	GPIO4_DIR = 0;
+	GPIO5_DIR = 0;
+	GPIO6_DIR = 0;
+	GPIO7_DIR = 0;
+	
+	/* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */
+	GPIO2_DIR |= (PIN_LED1 | PIN_LED2 | PIN_LED3);
+	
+	/* GPIO3[6] on P6_10  as output. */
+	GPIO3_DIR |= PIN_EN1V8;
+	
+	/* Configure SSP1 Peripheral (to be moved later in SSP driver) */
+	scu_pinmux(SCU_SSP1_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
+	scu_pinmux(SCU_SSP1_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
+	scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
+	scu_pinmux(SCU_SSP1_SSEL, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
+}
+
+void enable_1v8_power(void) {
+	gpio_set(PORT_EN1V8, PIN_EN1V8);
+}