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Disable CLK7 and power down CLK6/7 to reduce emissions

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This commit is contained in:
Dominic Spill
2017-02-20 12:34:35 -07:00
parent ef695a36e0
commit 3eb00ed0df
2 changed files with 12 additions and 35 deletions
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40
firmware/common/hackrf_core.c
View File

@ -490,60 +490,36 @@ void cpu_clock_init(void)
si5351c_configure_pll_sources(&clock_gen); si5351c_configure_pll_sources(&clock_gen);
si5351c_configure_pll_multisynth(&clock_gen); si5351c_configure_pll_multisynth(&clock_gen);
#if (defined JAWBREAKER || defined HACKRF_ONE)
/* /*
* Jawbreaker clocks: * Clocks:
* CLK0 -> MAX5864/CPLD * CLK0 -> MAX5864/CPLD
* CLK1 -> CPLD * CLK1 -> CPLD
* CLK2 -> SGPIO * CLK2 -> SGPIO
* CLK3 -> external clock output * CLK3 -> External Clock Output
* CLK4 -> RFFC5072 * CLK4 -> RFFC5072 (MAX2837 on rad1o)
* CLK5 -> MAX2837 * CLK5 -> MAX2837 (MAX2871 on rad1o)
* CLK6 -> none * CLK6 -> none
* CLK7 -> LPC4330 (but LPC4330 starts up on its own crystal) * CLK7 -> LPC43xx (uses a 12MHz crystal by default)
*/ */
/* MS3/CLK3 is the source for the external clock output. */ /* MS3/CLK3 is the source for the external clock output. */
si5351c_configure_multisynth(&clock_gen, 3, 80*128-512, 0, 1, 0); /* 800/80 = 10MHz */ si5351c_configure_multisynth(&clock_gen, 3, 80*128-512, 0, 1, 0); /* 800/80 = 10MHz */
#if (defined JAWBREAKER || defined HACKRF_ONE)
/* MS4/CLK4 is the source for the RFFC5071 mixer. */ /* MS4/CLK4 is the source for the RFFC5071 mixer. */
si5351c_configure_multisynth(&clock_gen, 4, 16*128-512, 0, 1, 0); /* 800/16 = 50MHz */ si5351c_configure_multisynth(&clock_gen, 4, 16*128-512, 0, 1, 0); /* 800/16 = 50MHz */
/* MS5/CLK5 is the source for the MAX2837 clock input. */ /* MS5/CLK5 is the source for the MAX2837 clock input. */
si5351c_configure_multisynth(&clock_gen, 5, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */ si5351c_configure_multisynth(&clock_gen, 5, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */
/* MS6/CLK6 is unused. */
/* MS7/CLK7 is the source for the LPC43xx microcontroller. */
uint8_t ms7data[] = { 90, 255, 20, 0 };
si5351c_write(&clock_gen, ms7data, sizeof(ms7data));
#endif #endif
#ifdef RAD1O #ifdef RAD1O
/* rad1o clocks:
* CLK0 -> MAX5864/CPLD
* CLK1 -> CPLD
* CLK2 -> SGPIO
* CLK3 -> External Clock Output
* CLK4 -> MAX2837
* CLK5 -> MAX2871
* CLK6 -> none
* CLK7 -> LPC4330 (but LPC4330 starts up on its own crystal) */
/* MS3/CLK3 is the source for the external clock output. */
si5351c_configure_multisynth(&clock_gen, 3, 80*128-512, 0, 1, 0); /* 800/80 = 10MHz */
/* MS4/CLK4 is the source for the MAX2837 clock input. */ /* MS4/CLK4 is the source for the MAX2837 clock input. */
si5351c_configure_multisynth(&clock_gen, 4, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */ si5351c_configure_multisynth(&clock_gen, 4, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */
/* MS5/CLK5 is the source for the RFFC5071 mixer. */ /* MS5/CLK5 is the source for the RFFC5071 mixer. */
si5351c_configure_multisynth(&clock_gen, 5, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */ si5351c_configure_multisynth(&clock_gen, 5, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */
#endif
/* MS6/CLK6 is unused. */ /* MS6/CLK6 is unused. */
/* MS7/CLK7 is unused. */
/* MS7/CLK7 is the source for the LPC43xx microcontroller. */
uint8_t ms7data[] = { 90, 255, 20, 0 };
si5351c_write(&clock_gen, ms7data, sizeof(ms7data));
#endif
/* Set to 10 MHz, the common rate between Jawbreaker and HackRF One. */ /* Set to 10 MHz, the common rate between Jawbreaker and HackRF One. */
sample_rate_set(10000000); sample_rate_set(10000000);

7
firmware/common/si5351c.c
View File

@ -184,7 +184,7 @@ void si5351c_configure_clock_control(si5351c_driver_t* const drv, const enum pll
,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_6MA) ,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_6MA)
,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_4MA) ,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_4MA)
,SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/ ,SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/
,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA) ,SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/
}; };
si5351c_write(drv, data, sizeof(data)); si5351c_write(drv, data, sizeof(data));
} }
@ -223,8 +223,9 @@ void si5351c_configure_clock_control(si5351c_driver_t* const drv, const enum pll
/* 3: External clock output is deactivated as it is not used and creates noise */ /* 3: External clock output is deactivated as it is not used and creates noise */
uint8_t data[] = { 3, ~((1 << 0) | (1 << 1) | (1 << 2) | (1 << 4) | (1 << 5))}; uint8_t data[] = { 3, ~((1 << 0) | (1 << 1) | (1 << 2) | (1 << 4) | (1 << 5))};
#else #else
/* Enable CLK outputs 0, 1, 2, 3, 4, 5, 7 only. */ /* Enable CLK outputs 0, 1, 2, 3, 4, 5. */
uint8_t data[] = { 3, 0x40 }; /* 7: Clock to CPU is deactivated as it is not used and creates noise */
uint8_t data[] = { 3, ~((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5))};
#endif #endif
si5351c_write(drv, data, sizeof(data)); si5351c_write(drv, data, sizeof(data));
} }