diff --git a/firmware/common/sgpio.c b/firmware/common/sgpio.c index b73b922d..42dfb902 100644 --- a/firmware/common/sgpio.c +++ b/firmware/common/sgpio.c @@ -20,6 +20,7 @@ * Boston, MA 02110-1301, USA. */ +#include #include #include @@ -41,9 +42,13 @@ void sgpio_configure_pin_functions() { scu_pinmux(SCU_PINMUX_SGPIO10, SCU_GPIO_FAST | SCU_CONF_FUNCTION6); scu_pinmux(SCU_PINMUX_SGPIO11, SCU_GPIO_FAST | SCU_CONF_FUNCTION6); scu_pinmux(SCU_PINMUX_SGPIO12, SCU_GPIO_FAST | SCU_CONF_FUNCTION6); - scu_pinmux(SCU_PINMUX_SGPIO13, SCU_GPIO_FAST | SCU_CONF_FUNCTION7); - scu_pinmux(SCU_PINMUX_SGPIO14, SCU_GPIO_FAST | SCU_CONF_FUNCTION7); - scu_pinmux(SCU_PINMUX_SGPIO15, SCU_GPIO_FAST | SCU_CONF_FUNCTION7); + scu_pinmux(SCU_PINMUX_SGPIO13, SCU_GPIO_FAST | SCU_CONF_FUNCTION4); /* GPIO5[12] */ + scu_pinmux(SCU_PINMUX_SGPIO14, SCU_GPIO_FAST | SCU_CONF_FUNCTION4); /* GPIO5[13] */ + scu_pinmux(SCU_PINMUX_SGPIO15, SCU_GPIO_FAST | SCU_CONF_FUNCTION4); /* GPIO5[14] */ + + sgpio_cpld_stream_rx_set_decimation(0); + + GPIO_DIR(GPIO5) |= GPIOPIN14 | GPIOPIN13 | GPIOPIN12; } @@ -238,3 +243,15 @@ void sgpio_cpld_stream_disable() { bool sgpio_cpld_stream_is_enabled() { return (SGPIO_GPIO_OUTREG & (1L << 10)) == 0; /* SGPIO10 */ } + +bool sgpio_cpld_stream_rx_set_decimation(const uint_fast8_t skip_n) { + /* CPLD interface is three bits, SGPIO[15:13]: + * 111: decimate by 1 (skip_n=0, skip no samples) + * 110: decimate by 2 (skip_n=1, skip every other sample) + * 101: decimate by 3 (skip_n=2, skip two of three samples) + * ... + * 000: decimate by 8 (skip_n=7, skip seven of eight samples) + */ + GPIO_SET(GPIO5) = GPIOPIN14 | GPIOPIN13 | GPIOPIN12; + GPIO_CLR(GPIO5) = (skip_n & 7) << 12; +} diff --git a/firmware/common/sgpio.h b/firmware/common/sgpio.h index d37ae4de..3f92c1bb 100644 --- a/firmware/common/sgpio.h +++ b/firmware/common/sgpio.h @@ -39,4 +39,6 @@ void sgpio_cpld_stream_enable(); void sgpio_cpld_stream_disable(); bool sgpio_cpld_stream_is_enabled(); +bool sgpio_cpld_stream_rx_set_decimation(const uint_fast8_t skip_n); + #endif//__SGPIO_H__ diff --git a/firmware/cpld/sgpio_if/default.xsvf b/firmware/cpld/sgpio_if/default.xsvf old mode 100755 new mode 100644 index 7bcbb905..33019898 Binary files a/firmware/cpld/sgpio_if/default.xsvf and b/firmware/cpld/sgpio_if/default.xsvf differ diff --git a/firmware/cpld/sgpio_if/top.jed b/firmware/cpld/sgpio_if/top.jed index 52f04961..44aa1403 100755 --- a/firmware/cpld/sgpio_if/top.jed +++ b/firmware/cpld/sgpio_if/top.jed @@ -1,5 +1,5 @@ Programmer Jedec Bit Map -Date Extracted: Sat Sep 21 23:00:53 2013 +Date Extracted: Tue Nov 19 16:33:01 2013 QF25812* QP100* @@ -12,20 +12,20 @@ N DEVICE XC2C64A-7-VQ100* Note Block 0 * Note Block 0 ZIA * -L000000 1111111111111111* -L000016 1111111111111111* +L000000 1111111011100111* +L000016 1110101011111111* L000032 1111111011110011* L000048 1111111111111111* L000064 1111111111111111* -L000080 1111111011010111* -L000096 1111111111111111* +L000080 1111111011100111* +L000096 1110101011111111* L000112 1111111111111111* -L000128 1111111111111111* +L000128 1110101011111111* L000144 1111111111111111* L000160 1111111111111111* L000176 1111111111111111* L000192 1111111111111111* -L000208 1111111111111111* +L000208 1111111011100111* L000224 1111111111111111* L000240 1111111111111111* L000256 1111111111111111* @@ -54,11 +54,11 @@ L000608 1111111111111111* L000624 1111111111111111* Note Block 0 PLA AND array * -L000640 11110111110111111111111111111111111111111111111111111111111111111111111111111111* -L000720 11111011111011111111111111111111111111111111111111111111111111111111111111111111* -L000800 11111111111111111111111111111111111111111111111111111111111111111111111111111111* -L000880 11111111111111111111111111111111111111111111111111111111111111111111111111111111* -L000960 11111111111111111111111111111111111111111111111111111111111111111111111111111111* +L000640 11010111111101110111111111011111111111111111111111111111111111111111111111111111* +L000720 11111011111111111111111111111111111111111111111111111111111111111111111111111111* +L000800 01011111111101110111111111111111111111111111111111111111111111111111111111111111* +L000880 11010111111011110111111111111111111111111111111111111111111111111111111111111111* +L000960 11010111111110110111111111111111111111111111111111111111111111111111111111111111* L001040 11111111111111111111111111111111111111111111111111111111111111111111111111111111* L001120 11111111111111111111111111111111111111111111111111111111111111111111111111111111* L001200 11111111111111111111111111111111111111111111111111111111111111111111111111111111* @@ -109,14 +109,14 @@ L004720 111111111111111111111111111111111111111111111111111111111111111111111111 L004800 11111111111111111111111111111111111111111111111111111111111111111111111111111111* L004880 11111111111111111111111111111111111111111111111111111111111111111111111111111111* L004960 11111111111111111111111111111111111111111111111111111111111111111111111111111111* -L005040 11111111111111111111111111111111111111111111111111111111111111111111111111111111* +L005040 11110111111111110111111111111111111111111111111111111111111111111111111111111111* Note Block 0 PLA OR array * L005120 1111111111111110* -L005136 1111111111111110* -L005152 1111111111111111* -L005168 1111111111111111* -L005184 1111111111111111* +L005136 1111111111111101* +L005152 1111111111111101* +L005168 1111111111111011* +L005184 1111111111111011* L005200 1111111111111111* L005216 1111111111111111* L005232 1111111111111111* @@ -184,9 +184,9 @@ L006259 000001111001111110011111100* L006286 000001111001111110011111100* L006313 000001111001111110011111100* L006340 000001111001111110011111100* -L006367 000001111001111110011111100* -L006394 000001111001111110011111100* -L006421 000001111001100110011111101* +L006367 000101111101110110011111100* +L006394 000101111101110111111111100* +L006421 000101111101110111011111100* Note Block 1 * Note Block 1 ZIA * @@ -374,15 +374,15 @@ L012928 1111111011110011* L012944 1111111111111111* L012960 1111111010110111* L012976 1111111011010111* -L012992 1111111010110111* -L013008 1111111011010111* -L013024 1111111010110111* +L012992 1110101011111111* +L013008 1100111011111111* +L013024 1110101011111111* L013040 1111111010110111* L013056 1111111010110111* -L013072 1111111011100111* -L013088 1111111011010111* +L013072 1111111011010111* +L013088 1111111010110111* L013104 1111111111111111* -L013120 1111111111111111* +L013120 1111111010110111* L013136 1111111011010111* L013152 1111111111111111* L013168 1111111111111111* @@ -392,7 +392,7 @@ L013216 1111111111111111* L013232 1111111111111111* L013248 1111111111111111* L013264 1111111111111111* -L013280 1111111111111111* +L013280 1111111011010111* L013296 1111111111111111* L013312 1111111111111111* L013328 1111111111111111* @@ -400,7 +400,7 @@ L013344 1111111111111111* L013360 1111111111111111* L013376 1111111111111111* L013392 1111111111111111* -L013408 1111111111111111* +L013408 1111111011100111* L013424 1111111111111111* L013440 1111111111111111* L013456 1111111111111111* @@ -410,27 +410,27 @@ L013504 1111111111111111* L013520 1111111111111111* Note Block 2 PLA AND array * -L013536 11111011111111111101111111111111111111111111111111111111111111111111111111111111* -L013616 11110111111111111110111111111111111111111111111111111111111111111111111111111111* -L013696 11111011111101111111111111111111111111111111111111111111111111111111111111111111* -L013776 11110111111110111111111111111111111111111111111111111111111111111111111111111111* -L013856 11111011011111111111111111111111111111111111111111111111111111111111111111111111* -L013936 11110111101111111111111111111111111111111111111111111111111111111111111111111111* -L014016 11111011111111110111111111111111111111111111111111111111111111111111111111111111* +L013536 11110111110111111111111111111111111111111111111111111111111111111011111111111111* +L013616 11011011111001110111111111111111111111111111111111111111111111111011111111111111* +L013696 11110111111011011111111111111111111111111111111111111111111111111111111111111111* +L013776 11111011110111011111111111111111111111111111111111111111111111111111111111111111* +L013856 11111011111111111101111111111111111111111111111111111111111111111111111111111111* +L013936 11110111111111111110111111111111111111111111111111111111111111111111111111111111* +L014016 11111011111111111111111111110111111111111111111111111111111111111111111111111111* L014096 11111111111011111111111111111111111111111111111111111111111111111111111111111111* -L014176 11110111111111111011111111111111111111111111111111111111111111111111111111111111* -L014256 11111011111111111111011111111111111111111111111111111111111111111111111111111111* -L014336 11011111111111111111111111111111111111111111111111111111111111111111111111111111* -L014416 11110111111111111111101111111111111111111111111111111111111111111111111111111111* -L014496 11111011111111011111111111111111111111111111111111111111111111111111111111111111* -L014576 11110111111111101111111111111111111111111111111111111111111111111111111111111111* -L014656 11111011111111111111111111111101111111111111111111111111111111111111111111111111* -L014736 11110111111111111111111111111110111111111111111111111111111111111111111111111111* -L014816 11111011111111111111111101111111111111111111111111111111111111111111111111111111* -L014896 11110111111111111111111110111111111111111111111111111111111111111111111111111111* -L014976 11111111111111111111111011111111111111111111111111111111111111111111111111111111* -L015056 11111111111111111111111111111111111111111111111111111111111111111111111111111111* -L015136 11111111111111111111111111111111111111111111111111111111111111111111111111111111* +L014176 11110111111111111111111111111011111111111111111111111111111111111111111111111111* +L014256 11111011011111111111111111111111111111111111111111111111111111111111111111111111* +L014336 11110111101111111111111111111111111111111111111111111111111111111111111111111111* +L014416 11111011111111111111111101111111111111111111111111111111111111111111111111111111* +L014496 11110111111111111111111110111111111111111111111111111111111111111111111111111111* +L014576 11111011111111111111011111111111111111111111111111111111111111111111111111111111* +L014656 11110111111111111111101111111111111111111111111111111111111111111111111111111111* +L014736 11111011111111111111110111111111111111111111111111111111111111111111111111111111* +L014816 11110111111111111111111011111111111111111111111111111111111111111111111111111111* +L014896 11111011111111111111111111111101111111111111111111111111111111111111111111111111* +L014976 11110111111111111111111111111110111111111111111111111111111111111111111111111111* +L015056 11111011111111111111111111111111111111111111111101111111111111111111111111111111* +L015136 11110111111111111111111111111111111111111111111110111111111111111111111111111111* L015216 11111111111111111111111111111111111111111111111111111111111111111111111111111111* L015296 11111111111111111111111111111111111111111111111111111111111111111111111111111111* L015376 11111111111111111111111111111111111111111111111111111111111111111111111111111111* @@ -468,27 +468,27 @@ L017856 111111111111111111111111111111111111111111111111111111111111111111111111 L017936 11111111111111111111111111111111111111111111111111111111111111111111111111111111* Note Block 2 PLA OR array * -L018016 1101111111111111* -L018032 1101111111111111* -L018048 1111011111111111* -L018064 1111011111111111* -L018080 1111111101111111* -L018096 1111111101111111* -L018112 1111111110111111* +L018016 0111111111111111* +L018032 0111111111111111* +L018048 0111111111111111* +L018064 0111111111111111* +L018080 1101111111111111* +L018096 1101111111111111* +L018112 1111011111111111* L018128 1111111111111111* -L018144 1111111110111111* -L018160 1111111111111011* -L018176 1111111111111111* -L018192 1111111111111011* -L018208 1111111111111101* -L018224 1111111111111101* -L018240 1111111111111110* -L018256 1111111111111110* -L018272 1111110111111111* -L018288 1111110111111111* -L018304 0111111111111111* -L018320 1111111111111111* -L018336 1111111111111111* +L018144 1111011111111111* +L018160 1111111101111111* +L018176 1111111101111111* +L018192 1111111110111111* +L018208 1111111110111111* +L018224 1111111111111011* +L018240 1111111111111011* +L018256 1111111111111101* +L018272 1111111111111101* +L018288 1111111111111110* +L018304 1111111111111110* +L018320 1111110111111111* +L018336 1111110111111111* L018352 1111111111111111* L018368 1111111111111111* L018384 1111111111111111* @@ -527,12 +527,12 @@ L018896 1111111111111111* Note Block 2 I/O Macrocell Configuration 27 bits * N Aclk ClkOp Clk:2 ClkFreq R:2 P:2 RegMod:2 INz:2 FB:2 InReg St XorIn:2 RegCom Oe:4 Tm Slw Pu* -L018912 000101111111111100000000011* -L018939 000001111001111110011111100* +L018912 000101111001110100000000011* +L018939 000001111000011100011111100* L018966 000101111000011101101000111* -L018993 000001111001111110011111100* +L018993 000001111000011100011111100* L019020 000101111000011101101000111* -L019047 000001111001111110011111100* +L019047 000001111000011100011111100* L019074 000101111000011100001000111* L019101 000001111000011100011111100* L019128 000101111000011101101000111* @@ -753,5 +753,5 @@ L025810 0* Note I/O Bank 1 Vcco * L025811 0* -C1565* -AA4D +C0D64* +AA1A diff --git a/firmware/cpld/sgpio_if/top.ucf b/firmware/cpld/sgpio_if/top.ucf index e03f0385..7fb009ba 100755 --- a/firmware/cpld/sgpio_if/top.ucf +++ b/firmware/cpld/sgpio_if/top.ucf @@ -54,7 +54,11 @@ NET "HOST_DATA<4>" LOC="67" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=to_host; NET "HOST_DATA<3>" LOC="72" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=to_host; NET "HOST_DATA<2>" LOC="74" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=to_host; NET "HOST_DATA<1>" LOC="79" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=to_host; -NET "HOST_DATA<0>" LOC="89" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=to_host; +NET "HOST_DATA<0>" LOC="89" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=to_host; + +NET "HOST_DECIM_SEL<2>" LOC="78" |IOSTANDARD=LVCMOS33; +NET "HOST_DECIM_SEL<1>" LOC="81" |IOSTANDARD=LVCMOS33; +NET "HOST_DECIM_SEL<0>" LOC="90" |IOSTANDARD=LVCMOS33; TIMEGRP "adc_data" OFFSET = IN 16 ns BEFORE "CODEC_X2_CLK"; diff --git a/firmware/cpld/sgpio_if/top.vhd b/firmware/cpld/sgpio_if/top.vhd index f431b246..90d6bb84 100755 --- a/firmware/cpld/sgpio_if/top.vhd +++ b/firmware/cpld/sgpio_if/top.vhd @@ -21,6 +21,7 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; +use ieee.std_logic_unsigned.all; library UNISIM; use UNISIM.vcomponents.all; @@ -30,7 +31,8 @@ entity top is HOST_DATA : inout std_logic_vector(7 downto 0); HOST_CAPTURE : out std_logic; HOST_DISABLE : in std_logic; - HOST_DIRECTION : in std_logic; + HOST_DIRECTION : in std_logic; + HOST_DECIM_SEL : in std_logic_vector(2 downto 0); DA : in std_logic_vector(7 downto 0); DD : out std_logic_vector(9 downto 0); @@ -57,6 +59,10 @@ architecture Behavioral of top is signal data_from_host_i : std_logic_vector(7 downto 0); signal data_to_host_o : std_logic_vector(7 downto 0); + signal decimate_count : std_logic_vector(2 downto 0) := "111"; + signal decimate_sel_i : std_logic_vector(2 downto 0); + signal decimate_en : std_logic; + begin ------------------------------------------------ @@ -87,9 +93,26 @@ begin host_data_enable_i <= not HOST_DISABLE; transfer_direction_i <= to_dac when HOST_DIRECTION = '1' else from_adc; - - ------------------------------------------------ - + + decimate_sel_i <= HOST_DECIM_SEL; + + ------------------------------------------------ + + decimate_en <= '1' when decimate_count = "111" else '0'; + + process(host_clk_i) + begin + if rising_edge(host_clk_i) then + if codec_clk_i = '1' then + if decimate_count = "111" then + decimate_count <= decimate_sel_i; + else + decimate_count <= decimate_count + 1; + end if; + end if; + end if; + end process; + process(host_clk_i) begin if rising_edge(host_clk_i) then @@ -123,7 +146,7 @@ begin end if; else if codec_clk_i = '0' then - host_data_capture_o <= host_data_enable_i; + host_data_capture_o <= host_data_enable_i and decimate_en; end if; end if; end if; diff --git a/firmware/cpld/sgpio_if/top_tb.vhd b/firmware/cpld/sgpio_if/top_tb.vhd index 3c15e9b2..6c38531b 100755 --- a/firmware/cpld/sgpio_if/top_tb.vhd +++ b/firmware/cpld/sgpio_if/top_tb.vhd @@ -1,22 +1,22 @@ -- --- Copyright 2012 Jared Boone --- --- This file is part of HackRF. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2, or (at your option) --- any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; see the file COPYING. If not, write to --- the Free Software Foundation, Inc., 51 Franklin Street, --- Boston, MA 02110-1301, USA. +-- Copyright 2012 Jared Boone +-- +-- This file is part of HackRF. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; see the file COPYING. If not, write to +-- the Free Software Foundation, Inc., 51 Franklin Street, +-- Boston, MA 02110-1301, USA. LIBRARY ieee; USE ieee.std_logic_1164.ALL; @@ -31,13 +31,12 @@ ARCHITECTURE behavior OF top_tb IS HOST_DATA : INOUT std_logic_vector(7 downto 0); HOST_CAPTURE : OUT std_logic; HOST_DISABLE : IN std_logic; - HOST_DIRECTION : IN std_logic; + HOST_DIRECTION : IN std_logic; + HOST_DECIM_SEL : IN std_logic_vector(2 downto 0); DA : IN std_logic_vector(7 downto 0); DD : OUT std_logic_vector(9 downto 0); CODEC_CLK : IN std_logic; - CODEC_X2_CLK : IN std_logic; - B1AUX : INOUT std_logic_vector(16 downto 9); - B2AUX : INOUT std_logic_vector(16 downto 1) + CODEC_X2_CLK : IN std_logic ); END COMPONENT; @@ -46,12 +45,11 @@ ARCHITECTURE behavior OF top_tb IS signal CODEC_CLK : std_logic := '0'; signal CODEC_X2_CLK : std_logic := '0'; signal HOST_DISABLE : std_logic := '1'; - signal HOST_DIRECTION : std_logic := '0'; + signal HOST_DIRECTION : std_logic := '0'; + signal HOST_DECIM_SEL : std_logic_vector(2 downto 0) := "010"; --BiDirs signal HOST_DATA : std_logic_vector(7 downto 0); - signal B1AUX : std_logic_vector(16 downto 9); - signal B2AUX : std_logic_vector(16 downto 1); --Outputs signal DD : std_logic_vector(9 downto 0); @@ -63,13 +61,12 @@ begin HOST_DATA => HOST_DATA, HOST_CAPTURE => HOST_CAPTURE, HOST_DISABLE => HOST_DISABLE, - HOST_DIRECTION => HOST_DIRECTION, + HOST_DIRECTION => HOST_DIRECTION, + HOST_DECIM_SEL => HOST_DECIM_SEL, DA => DA, DD => DD, CODEC_CLK => CODEC_CLK, - CODEC_X2_CLK => CODEC_X2_CLK, - B1AUX => B1AUX, - B2AUX => B2AUX + CODEC_X2_CLK => CODEC_X2_CLK ); clk_process :process @@ -90,11 +87,11 @@ begin begin wait until rising_edge(CODEC_CLK); wait for 9 ns; - DA <= (others => '0'); + DA <= "00000000"; wait until falling_edge(CODEC_CLK); wait for 9 ns; - DA <= (others => '1'); + DA <= "00000001"; end process; @@ -132,4 +129,4 @@ begin wait; end process; -end; +end; \ No newline at end of file