Sojus07/hackrf
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Corrected typo regarding SGPIO external clock configuration.

Browse Source
This commit is contained in:
Jared Boone
2012-07-24 13:29:03 -07:00
parent 4878be8213
commit 3593bee128
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
firmware/sgpio-rx/sgpio-rx.c
View File

@ -174,7 +174,7 @@ void configure_sgpio_test_tx() {
(3L << 5) | // QUALIFIER_MODE = 3 (external SGPIO pin) (3L << 5) | // QUALIFIER_MODE = 3 (external SGPIO pin)
(0L << 3) | // CLK_SOURCE_SLICE_MODE = X (0L << 3) | // CLK_SOURCE_SLICE_MODE = X
(0L << 1) | // CLK_SOURCE_PIN_MODE = 0 (SGPIO8) (0L << 1) | // CLK_SOURCE_PIN_MODE = 0 (SGPIO8)
(1L << 0); // EXT_CLK_ENABLE = 1, external clock signal (slice) (1L << 0); // EXT_CLK_ENABLE = 1, external clock signal
SGPIO_SLICE_MUX_CFG(SGPIO_SLICE_A) = SGPIO_SLICE_MUX_CFG(SGPIO_SLICE_A) =
(0L << 8) | // INV_QUALIFIER = 0 (use normal qualifier) (0L << 8) | // INV_QUALIFIER = 0 (use normal qualifier)
@ -254,7 +254,7 @@ void configure_sgpio_test_rx() {
(3L << 5) | // QUALIFIER_MODE = 3 (external SGPIO pin) (3L << 5) | // QUALIFIER_MODE = 3 (external SGPIO pin)
(0L << 3) | // CLK_SOURCE_SLICE_MODE = X (0L << 3) | // CLK_SOURCE_SLICE_MODE = X
(0L << 1) | // CLK_SOURCE_PIN_MODE = 0 (SGPIO8) (0L << 1) | // CLK_SOURCE_PIN_MODE = 0 (SGPIO8)
(1L << 0); // EXT_CLK_ENABLE = 1, external clock signal (slice) (1L << 0); // EXT_CLK_ENABLE = 1, external clock signal
SGPIO_SLICE_MUX_CFG(SGPIO_SLICE_A) = SGPIO_SLICE_MUX_CFG(SGPIO_SLICE_A) =
(0L << 8) | // INV_QUALIFIER = 0 (use normal qualifier) (0L << 8) | // INV_QUALIFIER = 0 (use normal qualifier)