Merge branch 'master' of https://github.com/mossmann/hackrf
This commit is contained in:
Jared Boone
10
firmware/sgpio_passthrough_rom_to_ram/Makefile
Normal file
10
firmware/sgpio_passthrough_rom_to_ram/Makefile
Normal file
@ -0,0 +1,10 @@
|
||||
# Hey Emacs, this is a -*- makefile -*-
|
||||
|
||||
BINARY = sgpio_passthrough
|
||||
|
||||
SRC = $(BINARY).c \
|
||||
../common/hackrf_core.c \
|
||||
../common/si5351c.c
|
||||
|
||||
LDSCRIPT = ../common/LPC4330_M4_rom_to_ram.ld
|
||||
include ../common/Makefile_inc.mk
|
||||
5
firmware/sgpio_passthrough_rom_to_ram/README
Normal file
5
firmware/sgpio_passthrough_rom_to_ram/README
Normal file
@ -0,0 +1,5 @@
|
||||
A program to test SGPIO with CPLD passthrough Input & Output via the SGPIO CPLD interface (P8 BANK2_AUX).
|
||||
For this test connect P10 BANK1_AUX AUX9 pin to +1V8 (in order to have P8 BANK2_AUX AUX1 to 16 as Output).
|
||||
This test requires:
|
||||
* JellyBean+Lemondrop(to set clock at 204MHz).
|
||||
* CPLD X2C64A hardware\jellybean\sgpio_if_passthrough\sgpio_if_passthrough.svf to be loaded first.
|
||||
BIN
firmware/sgpio_passthrough_rom_to_ram/Test_SGPIO0_to15.ods
Normal file
BIN
firmware/sgpio_passthrough_rom_to_ram/Test_SGPIO0_to15.ods
Normal file
Binary file not shown.
BIN
firmware/sgpio_passthrough_rom_to_ram/Test_SGPIO0_to15.pdf
Normal file
BIN
firmware/sgpio_passthrough_rom_to_ram/Test_SGPIO0_to15.pdf
Normal file
Binary file not shown.
@ -0,0 +1,68 @@
|
||||
|
||||
Test SGPIO GPIO mode, with LPC4330@204MHz (JellyBean+Lemondrop) and code executed in RAM.
|
||||
|
||||
Test1:
|
||||
------
|
||||
while(1)
|
||||
{
|
||||
for (uint_fast8_t i = 0; i < 8; i++)
|
||||
{
|
||||
SGPIO_GPIO_OUTREG ^= (1L << i);
|
||||
|
||||
}
|
||||
}
|
||||
Oscilloscope result (on SGPIO0): Frequency 750KHz => 272 cycles
|
||||
|
||||
Test2:
|
||||
------
|
||||
while(1)
|
||||
{
|
||||
__asm__(" nop");
|
||||
__asm__(" nop");
|
||||
__asm__(" nop");
|
||||
__asm__(" nop");
|
||||
__asm__(" nop");
|
||||
__asm__(" nop");
|
||||
__asm__(" nop");
|
||||
__asm__(" nop");
|
||||
__asm__(" nop");
|
||||
__asm__(" nop");
|
||||
__asm__(" nop");
|
||||
__asm__(" nop");
|
||||
SGPIO_GPIO_OUTREG ^= 0x5555;
|
||||
}
|
||||
Oscilloscope result (on SGPIO0): 3.923 MHz => 52 cycles
|
||||
|
||||
Test3:
|
||||
------
|
||||
while(1)
|
||||
{
|
||||
SGPIO_GPIO_OUTREG ^= 0x5555;
|
||||
}
|
||||
Oscilloscope result (on SGPIO0): Frequency 7.28MHz => 28 cycles
|
||||
|
||||
Test4:
|
||||
------
|
||||
while(1)
|
||||
{
|
||||
__asm__(" nop");
|
||||
__asm__(" nop");
|
||||
__asm__(" nop");
|
||||
__asm__(" nop");
|
||||
SGPIO_GPIO_OUTREG = 0x5555;
|
||||
__asm__(" nop");
|
||||
__asm__(" nop");
|
||||
__asm__(" nop");
|
||||
__asm__(" nop");
|
||||
SGPIO_GPIO_OUTREG = 0xAAAA;
|
||||
}
|
||||
Oscilloscope result (on SGPIO0): Frequency 17MHz => 12 cycles
|
||||
|
||||
Test5:
|
||||
------
|
||||
while(1)
|
||||
{
|
||||
SGPIO_GPIO_OUTREG = 0x5555;
|
||||
SGPIO_GPIO_OUTREG = 0xAAAA;
|
||||
}
|
||||
Oscilloscope result (on SGPIO0): Frequency 25.5MHz => 8 cycles
|
||||
419
firmware/sgpio_passthrough_rom_to_ram/sgpio_passthrough.c
Normal file
419
firmware/sgpio_passthrough_rom_to_ram/sgpio_passthrough.c
Normal file
@ -0,0 +1,419 @@
|
||||
/*
|
||||
* Copyright 2012 Michael Ossmann
|
||||
* Copyright (C) 2012 Jared Boone
|
||||
* Copyright (C) 2012 Benjamin Vernoux
|
||||
*
|
||||
* This file is part of HackRF.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include <libopencm3/lpc43xx/gpio.h>
|
||||
#include <libopencm3/lpc43xx/scu.h>
|
||||
#include <libopencm3/lpc43xx/sgpio.h>
|
||||
#include <libopencm3/lpc43xx/cgu.h>
|
||||
#include <libopencm3/cm3/scs.h>
|
||||
|
||||
#include <hackrf_core.h>
|
||||
|
||||
void pin_setup(void) {
|
||||
/* Configure SCU Pin Mux as GPIO */
|
||||
scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_PINMUX_LED3, SCU_GPIO_FAST);
|
||||
|
||||
scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_FAST);
|
||||
|
||||
/* Configure all GPIO as Input (safe state) */GPIO0_DIR = 0;
|
||||
GPIO1_DIR = 0;
|
||||
GPIO2_DIR = 0;
|
||||
GPIO3_DIR = 0;
|
||||
GPIO4_DIR = 0;
|
||||
GPIO5_DIR = 0;
|
||||
GPIO6_DIR = 0;
|
||||
GPIO7_DIR = 0;
|
||||
|
||||
/* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */
|
||||
GPIO2_DIR |= (PIN_LED1 | PIN_LED2 | PIN_LED3);
|
||||
|
||||
/* GPIO3[6] on P6_10 as output. */
|
||||
GPIO3_DIR |= PIN_EN1V8;
|
||||
|
||||
/* Configure SSP1 Peripheral (to be moved later in SSP driver) */
|
||||
scu_pinmux(SCU_SSP1_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
|
||||
scu_pinmux(SCU_SSP1_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
|
||||
scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
|
||||
scu_pinmux(SCU_SSP1_SSEL, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
|
||||
}
|
||||
|
||||
void enable_1v8_power() {
|
||||
gpio_set(PORT_EN1V8, PIN_EN1V8);
|
||||
}
|
||||
|
||||
void release_cpld_jtag_pins() {
|
||||
scu_pinmux(SCU_PINMUX_CPLD_TDO, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION4);
|
||||
scu_pinmux(SCU_PINMUX_CPLD_TCK, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
|
||||
scu_pinmux(SCU_PINMUX_CPLD_TMS, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
|
||||
scu_pinmux(SCU_PINMUX_CPLD_TDI, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
|
||||
|
||||
GPIO_DIR(PORT_CPLD_TDO) &= ~PIN_CPLD_TDO;
|
||||
GPIO_DIR(PORT_CPLD_TCK) &= ~PIN_CPLD_TCK;
|
||||
GPIO_DIR(PORT_CPLD_TMS) &= ~PIN_CPLD_TMS;
|
||||
GPIO_DIR(PORT_CPLD_TDI) &= ~PIN_CPLD_TDI;
|
||||
}
|
||||
|
||||
void configure_sgpio_pin_functions() {
|
||||
scu_pinmux(SCU_PINMUX_SGPIO0, SCU_GPIO_FAST | SCU_CONF_FUNCTION3);
|
||||
scu_pinmux(SCU_PINMUX_SGPIO1, SCU_GPIO_FAST | SCU_CONF_FUNCTION3);
|
||||
scu_pinmux(SCU_PINMUX_SGPIO2, SCU_GPIO_FAST | SCU_CONF_FUNCTION2);
|
||||
scu_pinmux(SCU_PINMUX_SGPIO3, SCU_GPIO_FAST | SCU_CONF_FUNCTION2);
|
||||
scu_pinmux(SCU_PINMUX_SGPIO4, SCU_GPIO_FAST | SCU_CONF_FUNCTION2);
|
||||
scu_pinmux(SCU_PINMUX_SGPIO5, SCU_GPIO_FAST | SCU_CONF_FUNCTION2);
|
||||
scu_pinmux(SCU_PINMUX_SGPIO6, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
|
||||
scu_pinmux(SCU_PINMUX_SGPIO7, SCU_GPIO_FAST | SCU_CONF_FUNCTION6);
|
||||
scu_pinmux(SCU_PINMUX_SGPIO8, SCU_GPIO_FAST | SCU_CONF_FUNCTION6);
|
||||
scu_pinmux(SCU_PINMUX_SGPIO9, SCU_GPIO_FAST | SCU_CONF_FUNCTION7);
|
||||
scu_pinmux(SCU_PINMUX_SGPIO10, SCU_GPIO_FAST | SCU_CONF_FUNCTION6);
|
||||
scu_pinmux(SCU_PINMUX_SGPIO11, SCU_GPIO_FAST | SCU_CONF_FUNCTION6);
|
||||
scu_pinmux(SCU_PINMUX_SGPIO12, SCU_GPIO_FAST | SCU_CONF_FUNCTION6);
|
||||
scu_pinmux(SCU_PINMUX_SGPIO13, SCU_GPIO_FAST | SCU_CONF_FUNCTION7);
|
||||
scu_pinmux(SCU_PINMUX_SGPIO14, SCU_GPIO_FAST | SCU_CONF_FUNCTION7);
|
||||
scu_pinmux(SCU_PINMUX_SGPIO15, SCU_GPIO_FAST | SCU_CONF_FUNCTION7);
|
||||
}
|
||||
|
||||
void test_sgpio_sliceA_D(void)
|
||||
{
|
||||
SGPIO_GPIO_OENREG = 0; // All inputs for the moment.
|
||||
|
||||
// Disable all counters during configuration
|
||||
SGPIO_CTRL_ENABLE = 0;
|
||||
|
||||
// Configure pin functions.
|
||||
configure_sgpio_pin_functions();
|
||||
|
||||
/****************************************************/
|
||||
/* Enable SGPIO pin outputs. */
|
||||
/****************************************************/
|
||||
SGPIO_GPIO_OENREG =
|
||||
0xFFFF; // data: output for SGPIO0 to SGPIO15
|
||||
|
||||
/*******************************************************************************/
|
||||
/* SGPIO pin 0 outputs slice A bit 0. (see Table 212. Output pin multiplexing) */
|
||||
/*******************************************************************************/
|
||||
SGPIO_OUT_MUX_CFG(0) =
|
||||
(0L << 4) | // P_OE_CFG = X
|
||||
(0L << 0); // P_OUT_CFG = 0, dout_doutm1 (1-bit mode)
|
||||
|
||||
// SGPIO pin 12 outputs slice D bit 0. (see Table 212. Output pin multiplexing)
|
||||
SGPIO_OUT_MUX_CFG(12) =
|
||||
(0L << 4) | // P_OE_CFG = X
|
||||
(0L << 0); // P_OUT_CFG = 0, dout_doutm1 (1-bit mode)
|
||||
|
||||
/****************************************************/
|
||||
/* Slice A */
|
||||
/****************************************************/
|
||||
SGPIO_MUX_CFG(SGPIO_SLICE_A) =
|
||||
(0L << 12) | // CONCAT_ORDER = 0 (self-loop)
|
||||
(1L << 11) | // CONCAT_ENABLE = 1 (concatenate data)
|
||||
(0L << 9) | // QUALIFIER_SLICE_MODE = X
|
||||
(0L << 7) | // QUALIFIER_PIN_MODE = X
|
||||
(0L << 5) | // QUALIFIER_MODE = 0 (enable)
|
||||
(0L << 3) | // CLK_SOURCE_SLICE_MODE = 0, slice D
|
||||
(0L << 1) | // CLK_SOURCE_PIN_MODE = X
|
||||
(0L << 0); // EXT_CLK_ENABLE = 0, internal clock signal (slice)
|
||||
|
||||
SGPIO_SLICE_MUX_CFG(SGPIO_SLICE_A) =
|
||||
(0L << 8) | // INV_QUALIFIER = 0 (use normal qualifier)
|
||||
(0L << 6) | // PARALLEL_MODE = 0 (shift 1 bit per clock)
|
||||
(0L << 4) | // DATA_CAPTURE_MODE = 0 (detect rising edge)
|
||||
(0L << 3) | // INV_OUT_CLK = 0 (normal clock)
|
||||
(0L << 2) | // CLKGEN_MODE = 0 (use clock from COUNTER)
|
||||
(0L << 1) | // CLK_CAPTURE_MODE = 0 (use rising clock edge)
|
||||
(0L << 0); // MATCH_MODE = 0 (do not match data)
|
||||
|
||||
SGPIO_PRESET(SGPIO_SLICE_A) = 1;
|
||||
SGPIO_COUNT(SGPIO_SLICE_A) = 0;
|
||||
SGPIO_POS(SGPIO_SLICE_A) = (0x1FL << 8) | (0x1FL << 0);
|
||||
SGPIO_REG(SGPIO_SLICE_A) = 0xAAAAAAAA; // Primary output data register
|
||||
SGPIO_REG_SS(SGPIO_SLICE_A) = 0xAAAAAAAA; // Shadow output data register
|
||||
|
||||
/****************************************************/
|
||||
/* Slice D (clock for Slice A) */
|
||||
/****************************************************/
|
||||
SGPIO_MUX_CFG(SGPIO_SLICE_D) =
|
||||
(0L << 12) | // CONCAT_ORDER = 0 (self-loop)
|
||||
(1L << 11) | // CONCAT_ENABLE = 1 (concatenate data)
|
||||
(0L << 9) | // QUALIFIER_SLICE_MODE = X
|
||||
(0L << 7) | // QUALIFIER_PIN_MODE = X
|
||||
(0L << 5) | // QUALIFIER_MODE = 0 (enable)
|
||||
(0L << 3) | // CLK_SOURCE_SLICE_MODE = 0, slice D
|
||||
(0L << 1) | // CLK_SOURCE_PIN_MODE = X
|
||||
(0L << 0); // EXT_CLK_ENABLE = 0, internal clock signal (slice)
|
||||
|
||||
SGPIO_SLICE_MUX_CFG(SGPIO_SLICE_D) =
|
||||
(0L << 8) | // INV_QUALIFIER = 0 (use normal qualifier)
|
||||
(0L << 6) | // PARALLEL_MODE = 0 (shift 1 bit per clock)
|
||||
(0L << 4) | // DATA_CAPTURE_MODE = 0 (detect rising edge)
|
||||
(0L << 3) | // INV_OUT_CLK = 0 (normal clock)
|
||||
(0L << 2) | // CLKGEN_MODE = 0 (use clock from COUNTER)
|
||||
(0L << 1) | // CLK_CAPTURE_MODE = 0 (use rising clock edge)
|
||||
(0L << 0); // MATCH_MODE = 0 (do not match data)
|
||||
|
||||
SGPIO_PRESET(SGPIO_SLICE_D) = 0;
|
||||
SGPIO_COUNT(SGPIO_SLICE_D) = 0;
|
||||
SGPIO_POS(SGPIO_SLICE_D) = (0x1FL << 8) | (0x1FL << 0);
|
||||
SGPIO_REG(SGPIO_SLICE_D) = 0xAAAAAAAA; // Primary output data register
|
||||
SGPIO_REG_SS(SGPIO_SLICE_D) = 0xAAAAAAAA; // Shadow output data register
|
||||
|
||||
|
||||
/****************************************************/
|
||||
/* Start SGPIO operation by enabling slice clocks. */
|
||||
/****************************************************/
|
||||
SGPIO_CTRL_ENABLE =
|
||||
(1L << SGPIO_SLICE_D) | // Slice D
|
||||
(1L << SGPIO_SLICE_A); // Slice A
|
||||
// Start SGPIO operation by enabling slice clocks.
|
||||
|
||||
/*
|
||||
Expected:
|
||||
SGPIO12 = MCU Freq/2
|
||||
SGPIO0 = SGPIO12/2 MHz= 51MHz (SliceD/2)
|
||||
*/
|
||||
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************/
|
||||
/* Output 1bit table (see Table 212. Output pin multiplexing) */
|
||||
/* SGPIO pin 00 outputs slice A bit 0. */
|
||||
/* SGPIO pin 01 outputs slice I bit 0. */
|
||||
/* SGPIO pin 02 outputs slice E bit 0. */
|
||||
/* SGPIO pin 03 outputs slice J bit 0. */
|
||||
/* SGPIO pin 04 outputs slice C bit 0. */
|
||||
/* SGPIO pin 05 outputs slice K bit 0. */
|
||||
/* SGPIO pin 06 outputs slice F bit 0. */
|
||||
/* SGPIO pin 07 outputs slice L bit 0. */
|
||||
/* SGPIO pin 08 outputs slice B bit 0. */
|
||||
/* SGPIO pin 09 outputs slice M bit 0. */
|
||||
/* SGPIO pin 10 outputs slice G bit 0. */
|
||||
/* SGPIO pin 11 outputs slice N bit 0. */
|
||||
/* SGPIO pin 12 outputs slice D bit 0. */
|
||||
/* SGPIO pin 13 outputs slice O bit 0. */
|
||||
/* SGPIO pin 14 outputs slice H bit 0. */
|
||||
/* SGPIO pin 15 outputs slice P bit 0. */
|
||||
/*******************************************************************************/
|
||||
const u8 slice_preset_tab[16] =
|
||||
{
|
||||
0, /* Idx00 = Slice A => SGPIO0 Freq Div by 1=0 */
|
||||
8, /* Idx01 = Slice B => SGPIO8 Freq Div by 9=8 */
|
||||
4, /* Idx02 = Slice C => SGPIO4 Freq Div by 5=4 */
|
||||
12, /* Idx03 = Slice D => SGPIO12 Freq Div by 13=12 */
|
||||
2, /* Idx04 = Slice E => SGPIO2 Freq Div by 3=2 */
|
||||
6, /* Idx05 = Slice F => SGPIO6 Freq Div by 7=6 */
|
||||
10, /* Idx06 = Slice G => SGPIO10 Freq Div by 11=10 */
|
||||
14, /* Idx07 = Slice H => SGPIO14 Freq Div by 15=14 */
|
||||
1, /* Idx08 = Slice I => SGPIO1 Freq Div by 2=1 */
|
||||
3, /* Idx09 = Slice J => SGPIO3 Freq Div by 4=3 */
|
||||
5, /* Idx10 = Slice K => SGPIO5 Freq Div by 6=5 */
|
||||
7, /* Idx11 = Slice L => SGPIO7 Freq Div by 8=7 */
|
||||
9, /* Idx12 = Slice M => SGPIO9 Freq Div by 10=9 */
|
||||
11, /* Idx13 = Slice N => SGPIO11 Freq Div by 12=11 */
|
||||
13, /* Idx14 = Slice O => SGPIO13 Freq Div by 14=13 */
|
||||
15 /* Idx15 = Slice P => SGPIO15 Freq Div by 16=15 */
|
||||
};
|
||||
|
||||
void test_sgpio_all_slices(void)
|
||||
{
|
||||
|
||||
SGPIO_GPIO_OENREG = 0; // All inputs for the moment.
|
||||
|
||||
// Disable all counters during configuration
|
||||
SGPIO_CTRL_ENABLE = 0;
|
||||
|
||||
// Configure pin functions.
|
||||
configure_sgpio_pin_functions();
|
||||
|
||||
/****************************************************/
|
||||
/* Enable SGPIO pin outputs. */
|
||||
/****************************************************/
|
||||
SGPIO_GPIO_OENREG =
|
||||
0xFFFF; // data: output for SGPIO0 to SGPIO15
|
||||
|
||||
for(uint_fast8_t i=0; i<16; i++)
|
||||
{
|
||||
SGPIO_OUT_MUX_CFG(i) =
|
||||
(0L << 4) | // P_OE_CFG = X
|
||||
(0L << 0); // P_OUT_CFG = 0, dout_doutm1 (1-bit mode)
|
||||
}
|
||||
|
||||
/****************************************************/
|
||||
/* Slice A to P */
|
||||
/****************************************************/
|
||||
for(uint_fast8_t i=0; i<16; i++)
|
||||
{
|
||||
SGPIO_MUX_CFG(i) =
|
||||
(0L << 12) | // CONCAT_ORDER = 0 (self-loop)
|
||||
(1L << 11) | // CONCAT_ENABLE = 1 (concatenate data)
|
||||
(0L << 9) | // QUALIFIER_SLICE_MODE = X
|
||||
(0L << 7) | // QUALIFIER_PIN_MODE = X
|
||||
(0L << 5) | // QUALIFIER_MODE = 0 (enable)
|
||||
(0L << 3) | // CLK_SOURCE_SLICE_MODE = 0, slice D
|
||||
(0L << 1) | // CLK_SOURCE_PIN_MODE = X
|
||||
(0L << 0); // EXT_CLK_ENABLE = 0, internal clock signal (slice)
|
||||
|
||||
SGPIO_SLICE_MUX_CFG(i) =
|
||||
(0L << 8) | // INV_QUALIFIER = 0 (use normal qualifier)
|
||||
(0L << 6) | // PARALLEL_MODE = 0 (shift 1 bit per clock)
|
||||
(0L << 4) | // DATA_CAPTURE_MODE = 0 (detect rising edge)
|
||||
(0L << 3) | // INV_OUT_CLK = 0 (normal clock)
|
||||
(0L << 2) | // CLKGEN_MODE = 0 (use clock from COUNTER)
|
||||
(0L << 1) | // CLK_CAPTURE_MODE = 0 (use rising clock edge)
|
||||
(0L << 0); // MATCH_MODE = 0 (do not match data)
|
||||
|
||||
SGPIO_PRESET(i) = slice_preset_tab[i];
|
||||
SGPIO_COUNT(i) = 0;
|
||||
SGPIO_POS(i) = (0x1FL << 8) | (0x1FL << 0);
|
||||
SGPIO_REG(i) = 0xAAAAAAAA; // Primary output data register
|
||||
SGPIO_REG_SS(i) = 0xAAAAAAAA; // Shadow output data register
|
||||
}
|
||||
|
||||
/****************************************************/
|
||||
/* Start SGPIO operation by enabling slice clocks. */
|
||||
/****************************************************/
|
||||
SGPIO_CTRL_ENABLE = 0xFFFF; /* Start all slices A to P */
|
||||
/*
|
||||
(1L << SGPIO_SLICE_D) | // Slice D
|
||||
(1L << SGPIO_SLICE_A); // Slice A
|
||||
// Start SGPIO operation by enabling slice clocks.
|
||||
*/
|
||||
/*
|
||||
Expected:
|
||||
MCU Freq MHz = 204
|
||||
SGPIO Theorical Freq MHz
|
||||
SGPIO00 = 102,00000
|
||||
SGPIO01 = 51,00000
|
||||
SGPIO02 = 34,00000
|
||||
SGPIO03 = 25,50000
|
||||
SGPIO04 = 20,40000
|
||||
SGPIO05 = 17,00000
|
||||
SGPIO06 = 14,57143
|
||||
SGPIO07 = 12,75000
|
||||
SGPIO08 = 11,33333
|
||||
SGPIO09 = 10,20000
|
||||
SGPIO10 = 9,27273
|
||||
SGPIO11 = 8,50000
|
||||
SGPIO12 = 7,84615
|
||||
SGPIO13 = 7,28571
|
||||
SGPIO14 = 6,80000
|
||||
SGPIO15 = 6,37500
|
||||
TitanMKD: I have problems with my boards and this test see document Test_SGPIO0_to15.ods / Test_SGPIO0_to15.pdf
|
||||
*/
|
||||
}
|
||||
|
||||
void test_sgpio_interface(void)
|
||||
{
|
||||
SGPIO_GPIO_OENREG = 0; // All inputs for the moment.
|
||||
|
||||
// Disable all counters during configuration
|
||||
SGPIO_CTRL_ENABLE = 0;
|
||||
|
||||
configure_sgpio_pin_functions();
|
||||
|
||||
// Make all SGPIO controlled by SGPIO's "GPIO" registers
|
||||
for (uint_fast8_t i = 0; i < 16; i++) {
|
||||
SGPIO_OUT_MUX_CFG(i) = (0L << 4) | (4L << 0);
|
||||
}
|
||||
|
||||
// Enable SGPIO pin outputs (SGPIO0 to 15).
|
||||
SGPIO_GPIO_OENREG = 0xFFFF;
|
||||
|
||||
/* Set values for SGPIO0 to 15 */
|
||||
while (1)
|
||||
{
|
||||
// 750KHz => 272 cycles
|
||||
/*
|
||||
for (uint_fast8_t i = 0; i < 8; i++) {
|
||||
SGPIO_GPIO_OUTREG ^= (1L << i);
|
||||
|
||||
}
|
||||
*/
|
||||
|
||||
// 3.923 MHz => 52 cycles
|
||||
__asm__(" nop");
|
||||
__asm__(" nop");
|
||||
__asm__(" nop");
|
||||
__asm__(" nop");
|
||||
__asm__(" nop");
|
||||
__asm__(" nop");
|
||||
__asm__(" nop");
|
||||
__asm__(" nop");
|
||||
__asm__(" nop");
|
||||
__asm__(" nop");
|
||||
__asm__(" nop");
|
||||
__asm__(" nop");
|
||||
SGPIO_GPIO_OUTREG ^= 0x5555;
|
||||
|
||||
// 7.28 MHz => 28 cycles
|
||||
/*
|
||||
SGPIO_GPIO_OUTREG ^= 0x5555;
|
||||
*/
|
||||
|
||||
// 17 MHz => 12 cycles
|
||||
/*
|
||||
__asm__(" nop");
|
||||
__asm__(" nop");
|
||||
__asm__(" nop");
|
||||
__asm__(" nop");
|
||||
SGPIO_GPIO_OUTREG = 0x5555;
|
||||
__asm__(" nop");
|
||||
__asm__(" nop");
|
||||
__asm__(" nop");
|
||||
__asm__(" nop");
|
||||
SGPIO_GPIO_OUTREG = 0xAAAA;
|
||||
*/
|
||||
// 25.50 MHz => 8 cycles
|
||||
/*
|
||||
SGPIO_GPIO_OUTREG = 0x5555;
|
||||
SGPIO_GPIO_OUTREG = 0xAAAA;
|
||||
*/
|
||||
}
|
||||
|
||||
/* TitanMKD: I have problems with my board with this test (see test_sgpio_all_slices()) */
|
||||
}
|
||||
|
||||
int main(void)
|
||||
{
|
||||
pin_setup();
|
||||
enable_1v8_power();
|
||||
cpu_clock_init();
|
||||
ssp1_init();
|
||||
|
||||
CGU_BASE_PERIPH_CLK = (CGU_BASE_CLK_AUTOBLOCK
|
||||
| (CGU_SRC_PLL1 << CGU_BASE_CLK_SEL_SHIFT));
|
||||
|
||||
CGU_BASE_APB1_CLK = (CGU_BASE_CLK_AUTOBLOCK
|
||||
| (CGU_SRC_PLL1 << CGU_BASE_CLK_SEL_SHIFT));
|
||||
|
||||
gpio_set(PORT_LED1_3, PIN_LED1);
|
||||
|
||||
//test_sgpio_sliceA_D();
|
||||
test_sgpio_interface();
|
||||
//test_sgpio_all_slices();
|
||||
|
||||
while(1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -1,4 +1,4 @@
|
||||
EESchema-LIBRARY Version 2.3 Date: Fri Jul 13 22:43:57 2012
|
||||
EESchema-LIBRARY Version 2.3 Date: Tue Jul 17 11:35:54 2012
|
||||
#encoding utf-8
|
||||
#
|
||||
# BALUN
|
||||
@ -117,6 +117,30 @@ X ~ 10 400 -200 300 L 60 60 1 1 P I
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# CONN_7X2
|
||||
#
|
||||
DEF CONN_7X2 P 0 40 Y N 1 F N
|
||||
F0 "P" 0 400 60 H V C CNN
|
||||
F1 "CONN_7X2" 0 0 60 V V C CNN
|
||||
DRAW
|
||||
S -100 350 100 -350 0 1 0 N
|
||||
X P1 1 -400 300 300 R 60 60 1 1 P I
|
||||
X P2 2 400 300 300 L 60 60 1 1 P I
|
||||
X P3 3 -400 200 300 R 60 60 1 1 P I
|
||||
X P4 4 400 200 300 L 60 60 1 1 P I
|
||||
X P5 5 -400 100 300 R 60 60 1 1 P I
|
||||
X P6 6 400 100 300 L 60 60 1 1 P I
|
||||
X P7 7 -400 0 300 R 60 60 1 1 P I
|
||||
X P8 8 400 0 300 L 60 60 1 1 P I
|
||||
X 9 9 -400 -100 300 R 60 60 1 1 P I
|
||||
X 10 10 400 -100 300 L 60 60 1 1 P I
|
||||
X 11 11 -400 -200 300 R 60 60 1 1 P I
|
||||
X 12 12 400 -200 300 L 60 60 1 1 P I
|
||||
X 13 13 -400 -300 300 R 60 60 1 1 P I
|
||||
X 14 14 400 -300 300 L 60 60 1 1 P I
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# DMC2400
|
||||
#
|
||||
DEF DMC2400 U 0 40 Y Y 1 F N
|
||||
@ -330,6 +354,23 @@ X INPUT 6 450 100 150 L 50 50 1 1 B
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# SKY13411
|
||||
#
|
||||
DEF SKY13411 U 0 40 Y Y 1 F N
|
||||
F0 "U" 0 0 60 H V C CNN
|
||||
F1 "SKY13411" 0 200 60 H V C CNN
|
||||
DRAW
|
||||
S -250 250 250 -250 0 1 0 N
|
||||
X GND 0 0 -550 300 U 50 50 1 1 W
|
||||
X ANT2 1 -550 100 300 R 50 50 1 1 B
|
||||
X V2 2 -550 0 300 R 50 50 1 1 I
|
||||
X RX 3 -550 -100 300 R 50 50 1 1 B
|
||||
X TX 4 550 -100 300 L 50 50 1 1 B
|
||||
X V1 5 550 0 300 L 50 50 1 1 I
|
||||
X ANT1 6 550 100 300 L 50 50 1 1 B
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# TRF3765
|
||||
#
|
||||
DEF TRF3765 U 0 40 Y Y 1 F N
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,4 +1,4 @@
|
||||
Cmp-Mod V01 Created by CvPCB (2011-06-30 BZR 3033)-stable date = Wed Jul 11 17:41:38 2012
|
||||
Cmp-Mod V01 Created by CvPCB (2011-06-30 BZR 3033)-stable date = Tue Jul 17 11:45:16 2012
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4FE2B60A;
|
||||
@ -491,44 +491,100 @@ IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4FF72FE3;
|
||||
TimeStamp = /50058DCC;
|
||||
Reference = C71;
|
||||
ValeurCmp = DNP;
|
||||
ValeurCmp = 220pF;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4FF72FE4;
|
||||
TimeStamp = /50058DC7;
|
||||
Reference = C72;
|
||||
ValeurCmp = DNP;
|
||||
ValeurCmp = 220pF;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4FF72FE5;
|
||||
TimeStamp = /50058F03;
|
||||
Reference = C73;
|
||||
ValeurCmp = DNP;
|
||||
ValeurCmp = 33pF;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4FF72FDF;
|
||||
TimeStamp = /50058F2C;
|
||||
Reference = C74;
|
||||
ValeurCmp = DNP;
|
||||
ValeurCmp = 33pF;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4FF72FDE;
|
||||
TimeStamp = /50058C0A;
|
||||
Reference = C75;
|
||||
ValeurCmp = DNP;
|
||||
ValeurCmp = 220pF;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4FF72E3F;
|
||||
TimeStamp = /50058BFA;
|
||||
Reference = C76;
|
||||
ValeurCmp = DNP;
|
||||
ValeurCmp = 220pF;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /50046E0E;
|
||||
Reference = C77;
|
||||
ValeurCmp = 220pF;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /50046E18;
|
||||
Reference = C78;
|
||||
ValeurCmp = 220pF;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /500474E3;
|
||||
Reference = C79;
|
||||
ValeurCmp = 33pF;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /50047438;
|
||||
Reference = C80;
|
||||
ValeurCmp = 33pF;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /50047399;
|
||||
Reference = C81;
|
||||
ValeurCmp = 220pF;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /50047390;
|
||||
Reference = C82;
|
||||
ValeurCmp = 220pF;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /500597A9;
|
||||
Reference = C83;
|
||||
ValeurCmp = 27pF;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /50059750;
|
||||
Reference = C84;
|
||||
ValeurCmp = 27pF;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
@ -645,10 +701,10 @@ IdModule = GSG-SMA-EDGE;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4FE0FACB;
|
||||
TimeStamp = /500592BA;
|
||||
Reference = P3;
|
||||
ValeurCmp = SERIAL;
|
||||
IdModule = GSG-HEADER-2x5;
|
||||
IdModule = GSG-HEADER-2x7;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
@ -680,10 +736,10 @@ IdModule = GSG-HEADER-2x5;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4FE10458;
|
||||
TimeStamp = /5005912D;
|
||||
Reference = P8;
|
||||
ValeurCmp = SWITCH_CTRL;
|
||||
IdModule = GSG-HEADER-2x5;
|
||||
IdModule = GSG-HEADER-2x7;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
@ -714,13 +770,6 @@ ValeurCmp = CONN_1;
|
||||
IdModule = GSG-HOLE-12MIL;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4FF72E05;
|
||||
Reference = R1;
|
||||
ValeurCmp = 0;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4FE0F4EE;
|
||||
Reference = R2;
|
||||
@ -735,20 +784,6 @@ ValeurCmp = 100;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4FF72E2A;
|
||||
Reference = R4;
|
||||
ValeurCmp = 0;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4FF72E0C;
|
||||
Reference = R5;
|
||||
ValeurCmp = 0;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4FE0F81D;
|
||||
Reference = R6;
|
||||
@ -763,13 +798,6 @@ ValeurCmp = 0;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4FF72E28;
|
||||
Reference = R8;
|
||||
ValeurCmp = 0;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4FE0F5B1;
|
||||
Reference = R9;
|
||||
@ -784,20 +812,6 @@ ValeurCmp = 100;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4FF72E0E;
|
||||
Reference = R11;
|
||||
ValeurCmp = 0;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4FF72E2F;
|
||||
Reference = R12;
|
||||
ValeurCmp = 0;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4FE0F80D;
|
||||
Reference = R13;
|
||||
@ -805,20 +819,6 @@ ValeurCmp = 10k;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4FF72E10;
|
||||
Reference = R14;
|
||||
ValeurCmp = 0;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4FF72E31;
|
||||
Reference = R15;
|
||||
ValeurCmp = 0;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4FE0DDD9;
|
||||
Reference = T1;
|
||||
@ -833,6 +833,13 @@ ValeurCmp = RX_BALUN;
|
||||
IdModule = GSG-B0310J50100AHF;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /50058BA6;
|
||||
Reference = T3;
|
||||
ValeurCmp = RX_LO_BALUN2;
|
||||
IdModule = GSG-B0310J50100AHF;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4FF61AF3;
|
||||
Reference = T4;
|
||||
@ -840,6 +847,13 @@ ValeurCmp = TX_BALUN;
|
||||
IdModule = GSG-B0310J50100AHF;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /50058C9F;
|
||||
Reference = T5;
|
||||
ValeurCmp = RX_LO_BALUN1;
|
||||
IdModule = GSG-B0310J50100AHF;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4FE0DF5A;
|
||||
Reference = T6;
|
||||
@ -847,6 +861,20 @@ ValeurCmp = TX_IF_BALUN;
|
||||
IdModule = GSG-2500BL14M100;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /50046DEA;
|
||||
Reference = T7;
|
||||
ValeurCmp = TX_LO_BALUN1;
|
||||
IdModule = GSG-B0310J50100AHF;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /50046EB3;
|
||||
Reference = T8;
|
||||
ValeurCmp = TX_LO_BALUN2;
|
||||
IdModule = GSG-B0310J50100AHF;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4FF07EB1;
|
||||
Reference = U1;
|
||||
@ -980,4 +1008,32 @@ ValeurCmp = NCP699;
|
||||
IdModule = SOT23-5;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /50058D81;
|
||||
Reference = U20;
|
||||
ValeurCmp = RX_LO_FILTER;
|
||||
IdModule = GSG-FI168B/L;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /50058CDB;
|
||||
Reference = U21;
|
||||
ValeurCmp = SKY13411;
|
||||
IdModule = GSG-SKY13411-374LF;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /500472E8;
|
||||
Reference = U22;
|
||||
ValeurCmp = SKY13411;
|
||||
IdModule = GSG-SKY13411-374LF;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /50046E65;
|
||||
Reference = U23;
|
||||
ValeurCmp = TX_LO_FILTER;
|
||||
IdModule = GSG-FI168B/L;
|
||||
EndCmp
|
||||
|
||||
EndListe
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
BIN
hardware/jellybean/JellyBean_pins.png
Normal file
BIN
hardware/jellybean/JellyBean_pins.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 3.2 MiB |
BIN
hardware/jellybean/jellybean_board_PCB_layers.pdf
Normal file
BIN
hardware/jellybean/jellybean_board_PCB_layers.pdf
Normal file
Binary file not shown.
BIN
hardware/jellybean/jellybean_schematic.pdf
Normal file
BIN
hardware/jellybean/jellybean_schematic.pdf
Normal file
Binary file not shown.
@ -1,4 +1,4 @@
|
||||
EESchema-DOCLIB Version 2.0 Date: Thu Jul 5 16:53:07 2012
|
||||
EESchema-DOCLIB Version 2.0 Date: Mon Jul 16 14:00:08 2012
|
||||
#
|
||||
$CMP GSG-DIODE-TVS-BI
|
||||
D Diode zener
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
EESchema-LIBRARY Version 2.3 Date: Thu Jul 5 16:53:07 2012
|
||||
EESchema-LIBRARY Version 2.3 Date: Mon Jul 16 14:00:08 2012
|
||||
#encoding utf-8
|
||||
#
|
||||
# BALUN
|
||||
@ -880,6 +880,23 @@ X VCTL1 6 600 100 300 L 50 50 1 1 I
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# SKY13411
|
||||
#
|
||||
DEF SKY13411 U 0 40 Y Y 1 F N
|
||||
F0 "U" 0 0 60 H V C CNN
|
||||
F1 "SKY13411" 0 200 60 H V C CNN
|
||||
DRAW
|
||||
S -250 250 250 -250 0 1 0 N
|
||||
X GND 0 0 -550 300 U 50 50 1 1 W
|
||||
X ANT2 1 -550 100 300 R 50 50 1 1 B
|
||||
X V2 2 -550 0 300 R 50 50 1 1 I
|
||||
X RX 3 -550 -100 300 R 50 50 1 1 B
|
||||
X TX 4 550 -100 300 L 50 50 1 1 B
|
||||
X V1 5 550 0 300 L 50 50 1 1 I
|
||||
X ANT1 6 550 100 300 L 50 50 1 1 B
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# TPS62410
|
||||
#
|
||||
DEF TPS62410 U 0 40 Y Y 1 F N
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
PCBNEW-LibModule-V1 Wed Jul 11 13:19:52 2012
|
||||
PCBNEW-LibModule-V1 Tue Jul 17 11:40:54 2012
|
||||
# encoding utf-8
|
||||
$INDEX
|
||||
GSG-HEADER-1x3
|
||||
@ -36,6 +36,8 @@ GSG-B0310J50100AHF
|
||||
GSG-SOT563
|
||||
GSG-SKY13350-385LF
|
||||
GSG-DFN6-3
|
||||
GSG-SKY13411-374LF
|
||||
GSG-FI168B/L
|
||||
$EndINDEX
|
||||
$INDEX
|
||||
GSG-QFN48-7
|
||||
@ -8051,4 +8053,160 @@ Po 0 0
|
||||
Le 33
|
||||
$EndPAD
|
||||
$EndMODULE GSG-DFN6-3
|
||||
$MODULE GSG-SKY13411-374LF
|
||||
Po 0 0 0 15 5005A0EF 00000000 ~~
|
||||
Li GSG-SKY13411-374LF
|
||||
Sc 00000000
|
||||
AR
|
||||
Op 0 0 0
|
||||
T0 0 0 197 118 0 30 N V 21 N "GSG-SKY13411-374LF"
|
||||
T1 0 0 197 118 0 30 N I 21 N "VAL**"
|
||||
DC -374 -374 -354 -354 80 21
|
||||
DS 295 -295 295 295 80 21
|
||||
DS 295 295 -295 295 80 21
|
||||
DS -295 295 -295 -295 80 21
|
||||
DS -295 -295 295 -295 80 21
|
||||
$PAD
|
||||
Sh "1" R 138 98 0 0 0
|
||||
Dr 0 0 0
|
||||
At SMD N 00888000
|
||||
Ne 0 ""
|
||||
Po -285 -197
|
||||
Le 41110432
|
||||
$EndPAD
|
||||
$PAD
|
||||
Sh "2" R 138 98 0 0 0
|
||||
Dr 0 0 0
|
||||
At SMD N 00888000
|
||||
Ne 0 ""
|
||||
Po -285 0
|
||||
Le 343506792
|
||||
$EndPAD
|
||||
$PAD
|
||||
Sh "3" R 138 98 0 0 0
|
||||
Dr 0 0 0
|
||||
At SMD N 00888000
|
||||
Ne 0 ""
|
||||
Po -285 197
|
||||
Le 41110432
|
||||
$EndPAD
|
||||
$PAD
|
||||
Sh "4" R 138 98 0 0 0
|
||||
Dr 0 0 0
|
||||
At SMD N 00888000
|
||||
Ne 0 ""
|
||||
Po 285 197
|
||||
Le 20
|
||||
$EndPAD
|
||||
$PAD
|
||||
Sh "5" R 138 98 0 0 0
|
||||
Dr 0 0 0
|
||||
At SMD N 00888000
|
||||
Ne 0 ""
|
||||
Po 285 0
|
||||
Le 4149
|
||||
$EndPAD
|
||||
$PAD
|
||||
Sh "6" R 138 98 0 0 0
|
||||
Dr 0 0 0
|
||||
At SMD N 00888000
|
||||
Ne 0 ""
|
||||
Po 285 -197
|
||||
Le 41110432
|
||||
$EndPAD
|
||||
$PAD
|
||||
Sh "0" R 79 512 0 0 0
|
||||
Dr 0 0 0
|
||||
At SMD N 00888000
|
||||
Ne 0 ""
|
||||
Po 0 0
|
||||
Le 41110432
|
||||
$EndPAD
|
||||
$PAD
|
||||
Sh "0" O 79 472 0 0 0
|
||||
Dr 0 0 0
|
||||
At SMD N 00888000
|
||||
Ne 0 ""
|
||||
Po 98 0
|
||||
Le 41110432
|
||||
$EndPAD
|
||||
$PAD
|
||||
Sh "0" R 197 472 0 0 0
|
||||
Dr 0 0 0
|
||||
At SMD N 00888000
|
||||
Ne 0 ""
|
||||
Po 0 0
|
||||
Le 41110432
|
||||
$EndPAD
|
||||
$PAD
|
||||
Sh "0" O 79 433 0 0 0
|
||||
Dr 0 0 0
|
||||
At SMD N 00888000
|
||||
Ne 0 ""
|
||||
Po -98 20
|
||||
Le 43999488
|
||||
$EndPAD
|
||||
$PAD
|
||||
Sh "0" R 28 56 0 0 -450
|
||||
Dr 0 0 0
|
||||
At SMD N 00888000
|
||||
Ne 0 ""
|
||||
Po -108 -207
|
||||
Le 343506792
|
||||
$EndPAD
|
||||
$PAD
|
||||
Sh "0" R 79 59 0 0 0
|
||||
Dr 0 0 0
|
||||
At SMD N 00888000
|
||||
Ne 0 ""
|
||||
Po -98 -167
|
||||
Le 343506680
|
||||
$EndPAD
|
||||
$EndMODULE GSG-SKY13411-374LF
|
||||
$MODULE GSG-FI168B/L
|
||||
Po 0 0 0 15 5005A33B 00000000 ~~
|
||||
Li GSG-FI168B/L
|
||||
Sc 00000000
|
||||
AR
|
||||
Op 0 0 0
|
||||
T0 0 0 157 118 0 30 N V 21 N "GSG-FI168B/L"
|
||||
T1 0 0 157 118 0 30 N I 21 N "VAL**"
|
||||
DS 315 -157 315 157 80 21
|
||||
DS 315 157 -315 157 80 21
|
||||
DS -315 157 -315 -157 80 21
|
||||
DS -315 -157 315 -157 80 21
|
||||
DC -177 0 -157 0 80 21
|
||||
$PAD
|
||||
Sh "1" R 197 118 0 0 0
|
||||
Dr 0 0 0
|
||||
At SMD N 00888000
|
||||
Ne 0 ""
|
||||
Po -335 0
|
||||
Le 1341
|
||||
$EndPAD
|
||||
$PAD
|
||||
Sh "3" R 197 118 0 0 0
|
||||
Dr 0 0 0
|
||||
At SMD N 00888000
|
||||
Ne 0 ""
|
||||
Po 335 0
|
||||
Le -1983002225
|
||||
$EndPAD
|
||||
$PAD
|
||||
Sh "4" R 315 197 0 0 0
|
||||
Dr 0 0 0
|
||||
At SMD N 00888000
|
||||
Ne 0 ""
|
||||
Po 0 -177
|
||||
Le -1954803880
|
||||
$EndPAD
|
||||
$PAD
|
||||
Sh "2" R 315 197 0 0 0
|
||||
Dr 0 0 0
|
||||
At SMD N 00888000
|
||||
Ne 0 ""
|
||||
Po 0 177
|
||||
Le 1341
|
||||
$EndPAD
|
||||
$EndMODULE GSG-FI168B/L
|
||||
$EndLIBRARY
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
EESchema-LIBRARY Version 2.3 Date: Thu Jun 21 18:47:05 2012
|
||||
EESchema-LIBRARY Version 2.3 Date: Sat Jun 30 17:09:21 2012
|
||||
#encoding utf-8
|
||||
#
|
||||
# BALUN
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
EESchema Schematic File Version 2 date Thu Jun 21 18:47:05 2012
|
||||
EESchema Schematic File Version 2 date Sat Jun 30 17:09:21 2012
|
||||
LIBS:power
|
||||
LIBS:device
|
||||
LIBS:transistors
|
||||
@ -37,7 +37,7 @@ $Descr User 17000 11000
|
||||
encoding utf-8
|
||||
Sheet 1 1
|
||||
Title ""
|
||||
Date "22 jun 2012"
|
||||
Date "30 jun 2012"
|
||||
Rev ""
|
||||
Comp ""
|
||||
Comment1 ""
|
||||
@ -45,7 +45,6 @@ Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 ""
|
||||
$EndDescr
|
||||
NoConn ~ 6500 5500
|
||||
Connection ~ 2200 7900
|
||||
Wire Wire Line
|
||||
2200 7900 2200 8000
|
||||
|
||||
Reference in New Issue
Block a user