diff --git a/firmware/common/hackrf_core.c b/firmware/common/hackrf_core.c
index 4b2cbf83..9cb6ec63 100644
--- a/firmware/common/hackrf_core.c
+++ b/firmware/common/hackrf_core.c
@@ -49,6 +49,19 @@ void cpu_clock_init(void)
 	si5351c_configure_pll_sources_for_xtal();
 	si5351c_configure_pll1_multisynth();
 
+#ifdef JELLYBEAN
+	/*
+	 * Jellybean/Lemondrop clocks:
+	 *   CLK0 -> MAX2837
+	 *   CLK1 -> MAX5864/CPLD
+	 *   CLK2 -> CPLD
+	 *   CLK3 -> CPLD
+	 *   CLK4 -> LPC4330
+	 *   CLK5 -> RFFC5072
+	 *   CLK6 -> extra
+	 *   CLK7 -> extra
+	 */
+
 	/* MS0/CLK0 is the source for the MAX2837 clock input. */
 	si5351c_configure_multisynth(0, 2048, 0, 1, 0); /* 40MHz */
 
@@ -66,6 +79,42 @@ void cpu_clock_init(void)
 
 	/* MS5/CLK5 is the source for the RFFC5071 mixer. */
 	si5351c_configure_multisynth(5, 1536, 0, 1, 0); /* 50MHz */
+#endif
+
+#ifdef JAWBREAKER
+	/*
+	 * Jawbreaker clocks:
+	 *   CLK0 -> MAX5864/CPLD
+	 *   CLK1 -> CPLD
+	 *   CLK2 -> SGPIO
+	 *   CLK3 -> external clock output
+	 *   CLK4 -> RFFC5072
+	 *   CLK5 -> MAX2837
+	 *   CLK6 -> none
+	 *   CLK7 -> LPC4330 (but LPC4330 starts up on its own crystal)
+	 */
+
+	/* MS0/CLK0 is the source for the MAX5864/CPLD (CODEC_CLK). */
+	si5351c_configure_multisynth(0, 4608, 0, 1, 1); /* 10MHz */
+
+	/* MS0/CLK1 is the source for the CPLD (CODEC_X2_CLK). */
+	si5351c_configure_multisynth(1, 4608, 0, 1, 0); /* 20MHz */
+
+	/* MS0/CLK2 is the source for SGPIO (CODEC_X2_CLK) */
+	si5351c_configure_multisynth(2, 4608, 0, 1, 0); /* 20MHz */
+
+	/* MS0/CLK3 is the source for the external clock output. */
+	si5351c_configure_multisynth(3, 4608, 0, 1, 0); /* 20MHz */
+
+	/* MS4/CLK4 is the source for the RFFC5071 mixer. */
+	si5351c_configure_multisynth(4, 1536, 0, 1, 0); /* 50MHz */
+
+	/* MS5/CLK5 is the source for the MAX2837 clock input. */
+	si5351c_configure_multisynth(5, 2048, 0, 1, 0); /* 40MHz */
+
+	/* MS7/CLK7 is the source for the LPC43xx microcontroller. */
+	//si5351c_configure_multisynth(7, 8021, 0, 3, 0); /* 12MHz */
+#endif
 
 	si5351c_configure_clock_control();
 	si5351c_enable_clock_outputs();
diff --git a/firmware/common/si5351c.c b/firmware/common/si5351c.c
index 5d7adf06..fa506150 100644
--- a/firmware/common/si5351c.c
+++ b/firmware/common/si5351c.c
@@ -161,6 +161,7 @@ void si5351c_configure_multisynth(const uint_fast8_t ms_number,
 	si5351c_write(data, sizeof(data));
 }
 
+#ifdef JELLYBEAN
 /*
  * Registers 16 through 23: CLKx Control
  * CLK0:
@@ -211,6 +212,66 @@ void si5351c_configure_clock_control()
 	uint8_t data[] = { 16, 0x4F, 0x4B, 0x4B, 0x4B, 0x0F, 0x4F, 0xC0, 0xC0 };
 	si5351c_write(data, sizeof(data));
 }
+#endif
+
+#ifdef JAWBREAKER
+/*
+ * Registers 16 through 23: CLKx Control
+ * CLK0:
+ *   CLK0_PDN=0 (powered up)
+ *   MS0_INT=1 (integer mode)
+ *   MS0_SRC=0 (PLLA as source for MultiSynth 0)
+ *   CLK0_INV=0 (not inverted)
+ *   CLK0_SRC=3 (MS0 as input source)
+ *   CLK0_IDRV=3 (8mA)
+ * CLK1:
+ *   CLK1_PDN=0 (powered up)
+ *   MS1_INT=1 (integer mode)
+ *   MS1_SRC=0 (PLLA as source for MultiSynth 1)
+ *   CLK1_INV=0 (not inverted)
+ *   CLK1_SRC=2 (MS0 as input source)
+ *   CLK1_IDRV=3 (8mA)
+ * CLK2:
+ *   CLK2_PDN=0 (powered up)
+ *   MS2_INT=1 (integer mode)
+ *   MS2_SRC=0 (PLLA as source for MultiSynth 2)
+ *   CLK2_INV=0 (not inverted)
+ *   CLK2_SRC=2 (MS0 as input source)
+ *   CLK2_IDRV=3 (8mA)
+ * CLK3:
+ *   CLK3_PDN=0 (powered up)
+ *   MS3_INT=1 (integer mode)
+ *   MS3_SRC=0 (PLLA as source for MultiSynth 3)
+ *   CLK3_INV=0 (inverted)
+ *   CLK3_SRC=2 (MS0 as input source)
+ *   CLK3_IDRV=3 (8mA)
+ * CLK4:
+ *   CLK4_PDN=0 (powered up)
+ *   MS4_INT=1 (integer mode)
+ *   MS4_SRC=0 (PLLA as source for MultiSynth 4)
+ *   CLK4_INV=0 (not inverted)
+ *   CLK4_SRC=3 (MS4 as input source)
+ *   CLK4_IDRV=3 (8mA)
+ * CLK5:
+ *   CLK5_PDN=0 (powered up)
+ *   MS5_INT=1 (integer mode)
+ *   MS5_SRC=0 (PLLA as source for MultiSynth 5)
+ *   CLK5_INV=0 (not inverted)
+ *   CLK5_SRC=3 (MS5 as input source)
+ *   CLK5_IDRV=3 (8mA)
+ * CLK6: (not connected)
+ *   CLK5_PDN=1 (powered down)
+ *   MS5_INT=1 (integer mode)
+ * CLK7: (not connected)
+ *   CLK7_PDN=1 (powered down)
+ *   MS7_INT=0 (fractional mode -- to support 12MHz to LPC)
+ */
+void si5351c_configure_clock_control()
+{
+	uint8_t data[] = { 16, 0x4F, 0x4B, 0x4B, 0x4B, 0x4F, 0x4F, 0xC0, 0x80 };
+	si5351c_write(data, sizeof(data));
+}
+#endif
 
 /* Enable CLK outputs 0, 1, 2, 3, 4, 5 only. */
 void si5351c_enable_clock_outputs()