Added two CGU debugging tools:

- check_clock.py to decode the frequency monitor result.
- dump_cgu.py to display selected CGU registers in a legible format.

firmware/tools/check_clock.py

@@ -0,0 +1,73 @@
+#!/usr/bin/env python
+
+# Copyright 2013 Jared Boone
+#
+# Interpret the LPC43xx Clock Generation Unit (CGU) FREQ_MON register
+# and display the estimated clock frequency.
+#
+# This file is part of HackRF.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; see the file COPYING.  If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+
+"""
+Inside GDB:
+	(gdb) set {int}0x40050014 = 0x09800000
+	(gdb) x 0x40050014
+	0x40050014:     0x091bd000
+This script:
+	./check_clock.py 0x<register value> 0x<RCNT initial value>
+"""
+
+import sys
+
+clock_source_names = {
+	0x00: '32 kHz oscillator',
+	0x01: 'IRC',
+	0x02: 'ENET_RX_CLK',
+	0x03: 'ENET_TX_CLK',
+	0x04: 'GP_CLKIN',
+	0x06: 'Crystal oscillator',
+	0x07: 'PLL0USB',
+	0x08: 'PLL0AUDIO',
+	0x09: 'PLL1',
+	0x0c: 'IDIVA',
+	0x0d: 'IDIVB',
+	0x0e: 'IDIVC',
+	0x0f: 'IDIVD',
+	0x10: 'IDIVE',
+}
+
+reg_value = int(sys.argv[1], 16)
+rcnt = int(sys.argv[2], 16)
+
+print('0x%08x' % reg_value)
+
+rcnt_final = reg_value & 0x1ff
+fcnt = (reg_value >> 9) & 0x3fff
+clock_source = (reg_value >> 24) & 0x1f
+fref = 12e6
+
+if rcnt_final != 0:
+	raise RuntimeError('RCNT did not reach 0')
+
+print('RCNT: %d' % rcnt)
+print('FCNT: %d' % fcnt)
+print('Fref: %d' % fref)
+
+clock_hz = fcnt / float(rcnt) * fref
+clock_mhz = clock_hz / 1e6
+clock_name = clock_source_names[clock_source] if clock_source in clock_source_names else 'Reserved'
+print('%s: %.3f MHz' % (clock_name, clock_mhz))

firmware/tools/dump_cgu.py

@@ -0,0 +1,145 @@
+#!/usr/bin/env python
+
+# Copyright 2013 Jared Boone
+#
+# Display the LPC43xx Clock Generation Unit (CGU) registers in an
+# easy-to-read format.
+#
+# This file is part of HackRF.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; see the file COPYING.  If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+
+"""
+In GDB:
+	dump binary memory cgu.bin 0x40050014 0x400500cc
+"""
+
+import sys
+from struct import unpack
+
+address = 0x40050014
+
+f = open('cgu.bin', 'read')
+d = '\x00' * 20 + f.read()
+length = len(d)
+f.close()
+
+def print_data(d):
+	for i in range(0, length, 16):
+		values = unpack('<IIII', d[i:i+16])
+		values = ['%08x' % v for v in values]
+		values_str = ' '.join(values)
+		line = '%08x: %s' % (address + i, values_str)
+		print(line)
+
+#print_data(d)
+#sys.exit(0)
+
+data = {}
+for i in range(0, length, 4):
+	data[i] = unpack('<I', d[i:i+4])[0]
+
+registers = {
+	0x14: {
+		'name': 'FREQ_MON',
+		'fields': (
+			('RCNT', 0, 9),
+			('FCNT', 9, 14),
+			('MEAS', 23, 1),
+			('CLK_SEL', 24, 5),
+		),
+	},
+	0x18: {
+		'name': 'XTAL_OSC_CONTROL',
+		'fields': (
+			('ENABLE', 0, 1),
+			('BYPASS', 1, 1),
+			('HF', 2, 1)
+		),
+	},
+	0x1c: {
+		'name': 'PLL0USB_STAT',
+		'fields': (
+			('LOCK', 0, 1),
+			('FR', 1, 1),
+		),
+	},
+	0x20: {
+		'name': 'PLL0USB_CTRL',
+		'fields': (
+			('PD', 0, 1),
+			('BYPASS', 1, 1),
+			('DIRECTI', 2, 1),
+			('DIRECTO', 3, 1),
+			('CLKEN', 4, 1),
+			('FRM', 6, 1),
+			('AUTOBLOCK', 11, 1),
+			('CLK_SEL', 24, 5),
+		),
+	},
+	0x24: {
+		'name': 'PLL0USB_MDIV',
+		'fields': (
+			('MDEC', 0, 17),
+			('SELP', 17, 5),
+			('SELI', 22, 6),
+			('SELR', 28, 4),
+		),
+	},
+	0x28: {
+		'name': 'PLL0USB_NP_DIV',
+		'fields': (
+			('PDEC', 0, 7),
+			('NDEC', 12, 10),
+		),
+	},
+	0x40: {
+		'name': 'PLL1_STAT',
+		'fields': (
+			('LOCK', 0, 1),
+		),
+	},
+	0x44: {
+		'name': 'PLL1_CTRL',
+		'fields': (
+			('PD', 0, 1),
+			('BYPASS', 1, 1),
+			('FBSEL', 6, 1),
+			('DIRECT', 7, 1),
+			('PSEL', 8, 2),
+			('AUTOBLOCK', 11, 1),
+			('NSEL', 12, 2),
+			('MSEL', 16, 8),
+			('CLK_SEL', 24, 5),
+		),
+	},
+	# TODO: Add other CGU registers. I did the ones that were
+	# valuable to me to debug CPU clock issues.
+}
+
+for address in sorted(registers):
+	register = registers[address]
+	name = register['name']
+	fields = register['fields']
+	value = data[address]
+	bits = bin(value)[2:].zfill(32)
+	print('%03x %20s %s = %08x' % (address, name, bits, value))
+	for field in fields:
+		name, low_bit, count = field
+		field_value = (value >> low_bit) & ((1 << count) - 1)
+		field_bits = bin(field_value)[2:].zfill(count) + ' ' * low_bit
+		field_bits = field_bits.rjust(32)
+		print('%03s %20s %s = %8x %s' % ('', '', field_bits, field_value, name))