diff --git a/firmware/common/hackrf_core.c b/firmware/common/hackrf_core.c
index cc07d054..9c4f9d52 100644
--- a/firmware/common/hackrf_core.c
+++ b/firmware/common/hackrf_core.c
@@ -555,10 +555,6 @@ void cpu_clock_init(void)
 	/* use IRC as clock source for APB3 */
 	CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_IRC);
 
-	/* Disable unused peripheral clocks */
-	CCU1_CLK_M4_EMC_CFG = 0;
-	CCU1_CLK_M4_EMCDIV_CFG = 0;
-
 	i2c_bus_start(clock_gen.bus, &i2c_config_si5351c_slow_clock);
 
 	si5351c_disable_all_outputs(&clock_gen);
@@ -712,6 +708,73 @@ void cpu_clock_init(void)
 
 	CGU_BASE_SSP1_CLK = CGU_BASE_SSP1_CLK_AUTOBLOCK(1)
 			| CGU_BASE_SSP1_CLK_CLK_SEL(CGU_SRC_PLL1);
+
+	/* Disable unused clocks */
+	/* Start with PLLs */
+	CGU_PLL0AUDIO_CTRL = CGU_PLL0AUDIO_CTRL_PD(1);
+
+	/* Dividers */
+	CGU_IDIVA_CTRL = CGU_IDIVA_CTRL_PD(1);
+	CGU_IDIVB_CTRL = CGU_IDIVB_CTRL_PD(1);
+	CGU_IDIVC_CTRL = CGU_IDIVC_CTRL_PD(1);
+	CGU_IDIVD_CTRL = CGU_IDIVD_CTRL_PD(1);
+	CGU_IDIVE_CTRL = CGU_IDIVE_CTRL_PD(1);
+
+	/* Base clocks */
+	CGU_BASE_SPIFI_CLK =  CGU_BASE_SPIFI_CLK_PD(1); /* SPIFI is only used at boot */
+	CGU_BASE_USB1_CLK = CGU_BASE_USB1_CLK_PD(1); /* USB1 is not exposed on HackRF */
+	CGU_BASE_PHY_RX_CLK = CGU_BASE_PHY_RX_CLK_PD(1);
+	CGU_BASE_PHY_TX_CLK = CGU_BASE_PHY_TX_CLK_PD(1);
+	CGU_BASE_LCD_CLK = CGU_BASE_LCD_CLK_PD(1);
+	CGU_BASE_VADC_CLK = CGU_BASE_VADC_CLK_PD(1);
+	CGU_BASE_SDIO_CLK = CGU_BASE_SDIO_CLK_PD(1);
+	CGU_BASE_UART0_CLK = CGU_BASE_UART0_CLK_PD(1);
+	CGU_BASE_UART1_CLK = CGU_BASE_UART1_CLK_PD(1);
+	CGU_BASE_UART2_CLK = CGU_BASE_UART2_CLK_PD(1);
+	CGU_BASE_UART3_CLK = CGU_BASE_UART3_CLK_PD(1);
+	CGU_BASE_OUT_CLK = CGU_BASE_OUT_CLK_PD(1);
+	CGU_BASE_AUDIO_CLK = CGU_BASE_AUDIO_CLK_PD(1);
+	CGU_BASE_CGU_OUT0_CLK = CGU_BASE_CGU_OUT0_CLK_PD(1);
+	CGU_BASE_CGU_OUT1_CLK = CGU_BASE_CGU_OUT1_CLK_PD(1);
+
+	/* Disable unused peripheral clocks */
+	CCU1_CLK_APB1_CAN1_CFG = 0;
+	CCU1_CLK_APB1_I2S_CFG = 0;
+	CCU1_CLK_APB1_MOTOCONPWM_CFG = 0;
+	CCU1_CLK_APB3_ADC0_CFG = 0;
+	CCU1_CLK_APB3_ADC1_CFG = 0;
+	CCU1_CLK_APB3_CAN0_CFG = 0;
+	CCU1_CLK_APB3_DAC_CFG = 0;
+	CCU1_CLK_M4_DMA_CFG = 0;
+	CCU1_CLK_M4_EMC_CFG = 0;
+	CCU1_CLK_M4_EMCDIV_CFG = 0;
+	CCU1_CLK_M4_ETHERNET_CFG = 0;
+	CCU1_CLK_M4_GPIO_CFG = 0;
+	CCU1_CLK_M4_LCD_CFG = 0;
+	CCU1_CLK_M4_QEI_CFG = 0;
+	CCU1_CLK_M4_RITIMER_CFG = 0;
+	CCU1_CLK_M4_SCT_CFG = 0;
+	CCU1_CLK_M4_SDIO_CFG = 0;
+	CCU1_CLK_M4_SPIFI_CFG = 0;
+	CCU1_CLK_M4_TIMER0_CFG = 0;
+	CCU1_CLK_M4_TIMER1_CFG = 0;
+	CCU1_CLK_M4_TIMER2_CFG = 0;
+	CCU1_CLK_M4_TIMER3_CFG = 0;
+	CCU1_CLK_M4_UART1_CFG = 0;
+	CCU1_CLK_M4_USART0_CFG = 0;
+	CCU1_CLK_M4_USART2_CFG = 0;
+	CCU1_CLK_M4_USART3_CFG = 0;
+	CCU1_CLK_M4_USB1_CFG = 0;
+	CCU1_CLK_M4_VADC_CFG = 0;
+	CCU1_CLK_SPIFI_CFG = 0;
+	CCU1_CLK_USB1_CFG = 0;
+	CCU1_CLK_VADC_CFG = 0;
+	CCU2_CLK_APB0_UART1_CFG = 0;
+	CCU2_CLK_APB0_USART0_CFG = 0;
+	CCU2_CLK_APB2_USART2_CFG = 0;
+	CCU2_CLK_APB2_USART3_CFG = 0;
+	CCU2_CLK_APLL_CFG = 0;
+	CCU2_CLK_SDIO_CFG = 0;
 }