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Consolidated two "deep" SGPIO configuration functions into one, qualified by transceiver mode (RX or TX). 95-ish % of the code was common.

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This commit is contained in:
Jared Boone
2012-10-11 15:18:16 -07:00
parent 6f0fda0bee
commit 1bad2d8536
3 changed files with 20 additions and 90 deletions
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101
firmware/common/sgpio.c
View File

@ -146,85 +146,6 @@ void sgpio_configure_for_tx() {
;
}
void sgpio_configure_for_tx_deep() {
// Disable all counters during configuration
SGPIO_CTRL_ENABLE = 0;
sgpio_configure_pin_functions();
// Set SGPIO output values.
SGPIO_GPIO_OUTREG =
(1L << 11) | // direction
(1L << 10); // disable
// Enable SGPIO pin outputs.
SGPIO_GPIO_OENREG =
(1L << 11) | // direction: TX: data to CPLD
(1L << 10) | // disable
(0L << 9) | // capture
(0L << 8) | // clock
0xFF; // data: output
SGPIO_OUT_MUX_CFG( 8) = 0; // SGPIO: Input: clock
SGPIO_OUT_MUX_CFG( 9) = 0; // SGPIO: Input: qualifier
SGPIO_OUT_MUX_CFG(10) = (0L << 4) | (4L << 0); // GPIO: Output: disable
SGPIO_OUT_MUX_CFG(11) = (0L << 4) | (4L << 0); // GPIO: Output: direction
for(uint_fast8_t i=0; i<8; i++) {
// SGPIO pin 0 outputs slice A bit "i".
SGPIO_OUT_MUX_CFG(i) =
(0L << 4) | // P_OE_CFG = 0
(11L << 0); // P_OUT_CFG = 11, dout_doutm8c (8-bit mode 8c)
}
const uint_fast8_t slice_indices[] = {
SGPIO_SLICE_A,
SGPIO_SLICE_I,
SGPIO_SLICE_E,
SGPIO_SLICE_J,
SGPIO_SLICE_C,
SGPIO_SLICE_K,
SGPIO_SLICE_F,
SGPIO_SLICE_L,
};
uint32_t slice_enable_mask = 0;
for(uint_fast8_t i=0; i<8; i++) {
uint_fast8_t slice_index = slice_indices[i];
const uint_fast8_t concat_order = 3;
const uint_fast8_t concat_enable = 1;
SGPIO_MUX_CFG(slice_index) =
(concat_order << 12) | // CONCAT_ORDER = 3 (eight slices)
(concat_enable << 11) | // CONCAT_ENABLE = 1 (concatenate data)
(0L << 9) | // QUALIFIER_SLICE_MODE = X
(1L << 7) | // QUALIFIER_PIN_MODE = 1 (SGPIO9)
(3L << 5) | // QUALIFIER_MODE = 3 (external SGPIO pin)
(0L << 3) | // CLK_SOURCE_SLICE_MODE = X
(0L << 1) | // CLK_SOURCE_PIN_MODE = 0 (SGPIO8)
(1L << 0); // EXT_CLK_ENABLE = 1, external clock signal (slice)
SGPIO_SLICE_MUX_CFG(slice_index) =
(0L << 8) | // INV_QUALIFIER = 0 (use normal qualifier)
(3L << 6) | // PARALLEL_MODE = 3 (shift 8 bits per clock)
(0L << 4) | // DATA_CAPTURE_MODE = 0 (detect rising edge)
(0L << 3) | // INV_OUT_CLK = X
(1L << 2) | // CLKGEN_MODE = 1 (use external pin clock)
(1L << 1) | // CLK_CAPTURE_MODE = 1 (use falling clock edge)
(0L << 0); // MATCH_MODE = 0 (do not match data)
SGPIO_PRESET(slice_index) = 0; // External clock, don't care
SGPIO_COUNT(slice_index) = 0; // External clock, don't care
SGPIO_POS(slice_index) = (0x1f << 8) | (0x1f << 0);
SGPIO_REG(slice_index) = 0xFFFFFFFF; // Primary output data register
SGPIO_REG_SS(slice_index) = 0xFFFFFFFF; // Shadow output data register
slice_enable_mask |= (1 << slice_index);
}
// Start SGPIO operation by enabling slice clocks.
SGPIO_CTRL_ENABLE = slice_enable_mask;
}
void sgpio_configure_for_rx() {
// Disable all counters during configuration
SGPIO_CTRL_ENABLE = 0;
@ -287,24 +208,30 @@ void sgpio_configure_for_rx() {
;
}
void sgpio_configure_for_rx_deep() {
void sgpio_configure_deep(const transceiver_mode_t transceiver_mode) {
// Disable all counters during configuration
SGPIO_CTRL_ENABLE = 0;
sgpio_configure_pin_functions();
// Set SGPIO output values.
const uint_fast8_t cpld_direction =
(transceiver_mode == TRANSCEIVER_MODE_TX) ? 1 : 0;
SGPIO_GPIO_OUTREG =
(0L << 11) | // direction
(cpld_direction << 11) | // direction
(1L << 10); // disable
// Enable SGPIO pin outputs.
const uint_fast16_t sgpio_gpio_data_direction =
(transceiver_mode == TRANSCEIVER_MODE_TX)
? (0xFF << 0)
: (0x00 << 0);
SGPIO_GPIO_OENREG =
(1L << 11) | // direction: RX: data from CPLD
(1L << 11) | // direction
(1L << 10) | // disable
(0L << 9) | // capture
(0L << 8) | // clock
0x00; // data: input
sgpio_gpio_data_direction; // data: output
SGPIO_OUT_MUX_CFG( 8) = 0; // SGPIO: Input: clock
SGPIO_OUT_MUX_CFG( 9) = 0; // SGPIO: Input: qualifier
@ -312,9 +239,10 @@ void sgpio_configure_for_rx_deep() {
SGPIO_OUT_MUX_CFG(11) = (0L << 4) | (4L << 0); // GPIO: Output: direction
for(uint_fast8_t i=0; i<8; i++) {
// SGPIO pin 0 outputs slice A bit "i".
SGPIO_OUT_MUX_CFG(i) =
(0L << 4) | // P_OE_CFG = 0
(9L << 0); // P_OUT_CFG = 9, dout_doutm8a (8-bit mode 8a)
(11L << 0); // P_OUT_CFG = 11, dout_doutm8c (8-bit mode 8c)
}
const uint_fast8_t slice_indices[] = {
@ -331,8 +259,9 @@ void sgpio_configure_for_rx_deep() {
uint32_t slice_enable_mask = 0;
for(uint_fast8_t i=0; i<8; i++) {
uint_fast8_t slice_index = slice_indices[i];
const uint_fast8_t concat_order = (slice_index == SGPIO_SLICE_A) ? 0 : 3;
const uint_fast8_t concat_enable = (slice_index == SGPIO_SLICE_A) ? 0 : 1;
const bool input_slice = (i == 0) && (transceiver_mode == TRANSCEIVER_MODE_RX);
const uint_fast8_t concat_order = input_slice ? 0 : 3;
const uint_fast8_t concat_enable = input_slice ? 0 : 1;
SGPIO_MUX_CFG(slice_index) =
(concat_order << 12) | // CONCAT_ORDER = 3 (eight slices)
(concat_enable << 11) | // CONCAT_ENABLE = 1 (concatenate data)

5
firmware/common/sgpio.h
View File

@ -22,12 +22,13 @@
#ifndef __SGPIO_H__
#define __SGPIO_H__
#include <hackrf_core.h>
void sgpio_configure_pin_functions();
void sgpio_test_interface();
void sgpio_configure_for_tx();
void sgpio_configure_for_tx_deep();
void sgpio_configure_for_rx();
void sgpio_configure_for_rx_deep();
void sgpio_configure_deep(const transceiver_mode_t transceiver_mode);
void sgpio_cpld_stream_enable();
void sgpio_cpld_stream_disable();
bool sgpio_cpld_stream_is_enabled();

4
firmware/usb_performance/usb_performance.c
View File

@ -205,10 +205,10 @@ bool usb_set_configuration(
// library.
if( device->configuration && (device->configuration->number == 1) ) {
if( transceiver_mode == TRANSCEIVER_MODE_RX ) {
sgpio_configure_for_rx_deep();
sgpio_configure_deep(transceiver_mode);
usb_endpoint_init(&usb_endpoint_bulk_in);
} else {
sgpio_configure_for_tx_deep();
sgpio_configure_deep(transceiver_mode);
usb_endpoint_init(&usb_endpoint_bulk_out);
}