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Merge branch 'master' into hygiene

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This commit is contained in:
Dominic Spill
2019-03-03 22:29:12 +00:00
committed by GitHub
parent 24fe561f3b a4c1ab65c6
commit 19f073fc5a
18 changed files with 347 additions and 234 deletions
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5
firmware/README
View File

@ -31,11 +31,6 @@ $ hackrf_spiflash -w hackrf_usb.bin
If you have a Jawbreaker, add -DBOARD=JAWBREAKER to the cmake command. If you have a Jawbreaker, add -DBOARD=JAWBREAKER to the cmake command.
If you have a rad1o, use -DBOARD=RAD1O instead. If you have a rad1o, use -DBOARD=RAD1O instead.
If you have a HackRF One and want to build optional PortaPack display support,
also specify -DUSER_INTERFACE=PORTAPACK. If PortaPack hardware is not detected
by hardware probing at start-up, the HackRF firmware will run without UI
support.
It is possible to use a USB Device Firmware Upgrade (DFU) method to load It is possible to use a USB Device Firmware Upgrade (DFU) method to load
firmware into RAM. This is normally only required to recover a device that has firmware into RAM. This is normally only required to recover a device that has
had faulty firmware loaded, but it can also be useful for firmware developers. had faulty firmware loaded, but it can also be useful for firmware developers.

6
firmware/common/cpld_jtag.c
View File

@ -35,14 +35,14 @@ void cpld_jtag_take(jtag_t* const jtag) {
/* Set initial GPIO state to the voltages of the internal or external pull-ups/downs, /* Set initial GPIO state to the voltages of the internal or external pull-ups/downs,
* to avoid any glitches. * to avoid any glitches.
*/ */
#ifdef USER_INTERFACE_PORTAPACK #ifdef HACKRF_ONE
gpio_set(gpio->gpio_pp_tms); gpio_set(gpio->gpio_pp_tms);
#endif #endif
gpio_set(gpio->gpio_tms); gpio_set(gpio->gpio_tms);
gpio_set(gpio->gpio_tdi); gpio_set(gpio->gpio_tdi);
gpio_clear(gpio->gpio_tck); gpio_clear(gpio->gpio_tck);
#ifdef USER_INTERFACE_PORTAPACK #ifdef HACKRF_ONE
/* Do not drive PortaPack-specific TMS pin initially, just to be cautious. */ /* Do not drive PortaPack-specific TMS pin initially, just to be cautious. */
gpio_input(gpio->gpio_pp_tms); gpio_input(gpio->gpio_pp_tms);
gpio_input(gpio->gpio_pp_tdo); gpio_input(gpio->gpio_pp_tdo);
@ -59,7 +59,7 @@ void cpld_jtag_release(jtag_t* const jtag) {
/* Make all pins inputs when JTAG interface not active. /* Make all pins inputs when JTAG interface not active.
* Let the pull-ups/downs do the work. * Let the pull-ups/downs do the work.
*/ */
#ifdef USER_INTERFACE_PORTAPACK #ifdef HACKRF_ONE
/* Do not drive PortaPack-specific pins, initially, just to be cautious. */ /* Do not drive PortaPack-specific pins, initially, just to be cautious. */
gpio_input(gpio->gpio_pp_tms); gpio_input(gpio->gpio_pp_tms);
gpio_input(gpio->gpio_pp_tdo); gpio_input(gpio->gpio_pp_tdo);

2
firmware/common/cpld_jtag.h
View File

@ -31,7 +31,7 @@ typedef struct jtag_gpio_t {
gpio_t gpio_tck; gpio_t gpio_tck;
gpio_t gpio_tdi; gpio_t gpio_tdi;
gpio_t gpio_tdo; gpio_t gpio_tdo;
#ifdef USER_INTERFACE_PORTAPACK #ifdef HACKRF_ONE
gpio_t gpio_pp_tms; gpio_t gpio_pp_tms;
gpio_t gpio_pp_tdo; gpio_t gpio_pp_tdo;
#endif #endif

87
firmware/common/hackrf-ui.c Normal file
View File

@ -0,0 +1,87 @@
/*
* Copyright (C) 2019 Jared Boone, ShareBrained Technology, Inc.
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#include "hackrf-ui.h"
#include "ui_portapack.h"
#include "ui_rad1o.h"
#include <stddef.h>
#define UNUSED(x) (void)(x)
/* Stub functions for null UI function table */
void hackrf_ui_init_null(void) { }
void hackrf_ui_set_frequency_null(uint64_t frequency) { UNUSED(frequency); }
void hackrf_ui_set_sample_rate_null(uint32_t sample_rate) { UNUSED(sample_rate); }
void hackrf_ui_set_direction_null(const rf_path_direction_t direction) { UNUSED(direction); }
void hackrf_ui_set_filter_bw_null(uint32_t bandwidth) { UNUSED(bandwidth); }
void hackrf_ui_set_lna_power_null(bool lna_on) { UNUSED(lna_on); }
void hackrf_ui_set_bb_lna_gain_null(const uint32_t gain_db) { UNUSED(gain_db); }
void hackrf_ui_set_bb_vga_gain_null(const uint32_t gain_db) { UNUSED(gain_db); }
void hackrf_ui_set_bb_tx_vga_gain_null(const uint32_t gain_db) { UNUSED(gain_db); }
void hackrf_ui_set_first_if_frequency_null(const uint64_t frequency) { UNUSED(frequency); }
void hackrf_ui_set_filter_null(const rf_path_filter_t filter) { UNUSED(filter); }
void hackrf_ui_set_antenna_bias_null(bool antenna_bias) { UNUSED(antenna_bias); }
/* Null UI function table, used if there's no hardware UI detected. Eliminates the
* need to check for null UI before calling a function in the table.
*/
static const hackrf_ui_t hackrf_ui_null = {
&hackrf_ui_init_null,
&hackrf_ui_set_frequency_null,
&hackrf_ui_set_sample_rate_null,
&hackrf_ui_set_direction_null,
&hackrf_ui_set_filter_bw_null,
&hackrf_ui_set_lna_power_null,
&hackrf_ui_set_bb_lna_gain_null,
&hackrf_ui_set_bb_vga_gain_null,
&hackrf_ui_set_bb_tx_vga_gain_null,
&hackrf_ui_set_first_if_frequency_null,
&hackrf_ui_set_filter_null,
&hackrf_ui_set_antenna_bias_null,
};
const hackrf_ui_t* portapack_detect(void) __attribute__((weak));
const hackrf_ui_t* rad1o_ui_setup(void) __attribute__((weak));
static const hackrf_ui_t* ui = NULL;
const hackrf_ui_t* hackrf_ui(void) {
/* Detect on first use. If no UI hardware is detected, use a stub function table. */
if( ui == NULL ) {
#ifdef HACKRF_ONE
if( portapack_detect ) {
ui = portapack_detect();
}
#endif
#ifdef RAD1O
if( rad1o_ui_setup ) {
ui = rad1o_ui_setup();
}
#endif
}
if( ui == NULL ) {
ui = &hackrf_ui_null;
}
return ui;
}

37
firmware/common/hackrf-ui.h
View File

@ -1,3 +1,24 @@
/*
* Copyright (C) 2018 Jared Boone, ShareBrained Technology, Inc.
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#ifndef HACKRF_UI_H #ifndef HACKRF_UI_H
#define HACKRF_UI_H #define HACKRF_UI_H
@ -36,20 +57,6 @@ typedef struct {
* In the future, whatever UI was detected will be returned here, * In the future, whatever UI was detected will be returned here,
* or NULL if no UI was detected. * or NULL if no UI was detected.
*/ */
const hackrf_ui_t* hackrf_ui(void) __attribute__((weak)); const hackrf_ui_t* hackrf_ui(void);
void hackrf_ui_init(void) __attribute__((weak));
void hackrf_ui_setFrequency(uint64_t _freq) __attribute__((weak));
void hackrf_ui_setSampleRate(uint32_t _sample_rate) __attribute__((weak));
void hackrf_ui_setDirection(const rf_path_direction_t _direction) __attribute__((weak));
void hackrf_ui_setFilterBW(uint32_t bw) __attribute__((weak));
void hackrf_ui_setLNAPower(bool _lna_on) __attribute__((weak));
void hackrf_ui_setBBLNAGain(const uint32_t gain_db) __attribute__((weak));
void hackrf_ui_setBBVGAGain(const uint32_t gain_db) __attribute__((weak));
void hackrf_ui_setBBTXVGAGain(const uint32_t gain_db) __attribute__((weak));
void hackrf_ui_setFirstIFFrequency(const uint64_t freq) __attribute__((weak));
void hackrf_ui_setFilter(const rf_path_filter_t filter) __attribute__((weak));
void hackrf_ui_setAntennaBias(bool antenna_bias) __attribute__((weak));
#endif #endif

175
firmware/common/hackrf_core.c
View File

@ -124,7 +124,7 @@ static struct gpio_t gpio_cpld_tms = GPIO(3, 1);
static struct gpio_t gpio_cpld_tdi = GPIO(3, 4); static struct gpio_t gpio_cpld_tdi = GPIO(3, 4);
#endif #endif
#ifdef USER_INTERFACE_PORTAPACK #ifdef HACKRF_ONE
static struct gpio_t gpio_cpld_pp_tms = GPIO(1, 1); static struct gpio_t gpio_cpld_pp_tms = GPIO(1, 1);
static struct gpio_t gpio_cpld_pp_tdo = GPIO(1, 8); static struct gpio_t gpio_cpld_pp_tdo = GPIO(1, 8);
#endif #endif
@ -146,9 +146,9 @@ i2c_bus_t i2c1 = {
.transfer = i2c_lpc_transfer, .transfer = i2c_lpc_transfer,
}; };
const i2c_lpc_config_t i2c_config_si5351c_slow_clock = { // const i2c_lpc_config_t i2c_config_si5351c_slow_clock = {
.duty_cycle_count = 15, // .duty_cycle_count = 15,
}; // };
const i2c_lpc_config_t i2c_config_si5351c_fast_clock = { const i2c_lpc_config_t i2c_config_si5351c_fast_clock = {
.duty_cycle_count = 255, .duty_cycle_count = 255,
@ -276,7 +276,7 @@ jtag_gpio_t jtag_gpio_cpld = {
.gpio_tck = &gpio_cpld_tck, .gpio_tck = &gpio_cpld_tck,
.gpio_tdi = &gpio_cpld_tdi, .gpio_tdi = &gpio_cpld_tdi,
.gpio_tdo = &gpio_cpld_tdo, .gpio_tdo = &gpio_cpld_tdo,
#ifdef USER_INTERFACE_PORTAPACK #ifdef HACKRF_ONE
.gpio_pp_tms = &gpio_cpld_pp_tms, .gpio_pp_tms = &gpio_cpld_pp_tms,
.gpio_pp_tdo = &gpio_cpld_pp_tdo, .gpio_pp_tdo = &gpio_cpld_pp_tdo,
#endif #endif
@ -337,7 +337,7 @@ bool sample_rate_frac_set(uint32_t rate_num, uint32_t rate_denom)
uint32_t a, b, c; uint32_t a, b, c;
uint32_t rem; uint32_t rem;
hackrf_ui_setSampleRate(rate_num/2); hackrf_ui()->set_sample_rate(rate_num/2);
/* Find best config */ /* Find best config */
a = (VCO_FREQ * rate_denom) / rate_num; a = (VCO_FREQ * rate_denom) / rate_num;
@ -458,11 +458,68 @@ bool sample_rate_set(const uint32_t sample_rate_hz) {
bool baseband_filter_bandwidth_set(const uint32_t bandwidth_hz) { bool baseband_filter_bandwidth_set(const uint32_t bandwidth_hz) {
uint32_t bandwidth_hz_real = max2837_set_lpf_bandwidth(&max2837, bandwidth_hz); uint32_t bandwidth_hz_real = max2837_set_lpf_bandwidth(&max2837, bandwidth_hz);
if(bandwidth_hz_real) hackrf_ui_setFilterBW(bandwidth_hz_real); if(bandwidth_hz_real) hackrf_ui()->set_filter_bw(bandwidth_hz_real);
return bandwidth_hz_real != 0; return bandwidth_hz_real != 0;
} }
/*
Configure PLL1 (Main MCU Clock) to max speed (204MHz).
Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1.
This function shall be called after cpu_clock_init().
*/
static void cpu_clock_pll1_max_speed(void)
{
uint32_t pll_reg;
/* Configure PLL1 to Intermediate Clock (between 90 MHz and 110 MHz) */
/* Integer mode:
FCLKOUT = M*(FCLKIN/N)
FCCO = 2*P*FCLKOUT = 2*P*M*(FCLKIN/N)
*/
pll_reg = CGU_PLL1_CTRL;
/* Clear PLL1 bits */
pll_reg &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK | CGU_PLL1_CTRL_PD_MASK | CGU_PLL1_CTRL_FBSEL_MASK | /* CLK SEL, PowerDown , FBSEL */
CGU_PLL1_CTRL_BYPASS_MASK | /* BYPASS */
CGU_PLL1_CTRL_DIRECT_MASK | /* DIRECT */
CGU_PLL1_CTRL_PSEL_MASK | CGU_PLL1_CTRL_MSEL_MASK | CGU_PLL1_CTRL_NSEL_MASK ); /* PSEL, MSEL, NSEL- divider ratios */
/* Set PLL1 up to 12MHz * 8 = 96MHz. */
pll_reg |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL)
| CGU_PLL1_CTRL_PSEL(0)
| CGU_PLL1_CTRL_NSEL(0)
| CGU_PLL1_CTRL_MSEL(7)
| CGU_PLL1_CTRL_FBSEL(1);
CGU_PLL1_CTRL = pll_reg;
/* wait until stable */
while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK_MASK));
/* use PLL1 as clock source for BASE_M4_CLK (CPU) */
CGU_BASE_M4_CLK = (CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_PLL1) | CGU_BASE_M4_CLK_AUTOBLOCK(1));
/* Wait before to switch to max speed */
delay(WAIT_CPU_CLOCK_INIT_DELAY);
/* Configure PLL1 Max Speed */
/* Direct mode: FCLKOUT = FCCO = M*(FCLKIN/N) */
pll_reg = CGU_PLL1_CTRL;
/* Clear PLL1 bits */
pll_reg &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK | CGU_PLL1_CTRL_PD_MASK | CGU_PLL1_CTRL_FBSEL_MASK | /* CLK SEL, PowerDown , FBSEL */
CGU_PLL1_CTRL_BYPASS_MASK | /* BYPASS */
CGU_PLL1_CTRL_DIRECT_MASK | /* DIRECT */
CGU_PLL1_CTRL_PSEL_MASK | CGU_PLL1_CTRL_MSEL_MASK | CGU_PLL1_CTRL_NSEL_MASK ); /* PSEL, MSEL, NSEL- divider ratios */
/* Set PLL1 up to 12MHz * 17 = 204MHz. */
pll_reg |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL)
| CGU_PLL1_CTRL_PSEL(0)
| CGU_PLL1_CTRL_NSEL(0)
| CGU_PLL1_CTRL_MSEL(16)
| CGU_PLL1_CTRL_FBSEL(1)
| CGU_PLL1_CTRL_DIRECT(1);
CGU_PLL1_CTRL = pll_reg;
/* wait until stable */
while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK_MASK));
}
/* clock startup for LPC4320 configure PLL1 to max speed (204MHz). /* clock startup for LPC4320 configure PLL1 to max speed (204MHz).
Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1. */ Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1. */
void cpu_clock_init(void) void cpu_clock_init(void)
@ -473,7 +530,7 @@ void cpu_clock_init(void)
/* use IRC as clock source for APB3 */ /* use IRC as clock source for APB3 */
CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_IRC); CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_IRC);
i2c_bus_start(clock_gen.bus, &i2c_config_si5351c_slow_clock); i2c_bus_start(clock_gen.bus, &i2c_config_si5351c_fast_clock);
si5351c_disable_all_outputs(&clock_gen); si5351c_disable_all_outputs(&clock_gen);
si5351c_disable_oeb_pin_control(&clock_gen); si5351c_disable_oeb_pin_control(&clock_gen);
@ -543,10 +600,7 @@ void cpu_clock_init(void)
CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_AUTOBLOCK(1) CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_AUTOBLOCK(1)
| CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_XTAL); | CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_XTAL);
cpu_clock_pll1_low_speed(); cpu_clock_pll1_max_speed();
/* use PLL1 as clock source for BASE_M4_CLK (CPU) */
CGU_BASE_M4_CLK = (CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_PLL1) | CGU_BASE_M4_CLK_AUTOBLOCK(1));
/* use XTAL_OSC as clock source for PLL0USB */ /* use XTAL_OSC as clock source for PLL0USB */
CGU_PLL0USB_CTRL = CGU_PLL0USB_CTRL_PD(1) CGU_PLL0USB_CTRL = CGU_PLL0USB_CTRL_PD(1)
@ -658,97 +712,6 @@ void cpu_clock_init(void)
#endif #endif
} }
/*
Configure PLL1 to low speed (48MHz).
Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1.
This function shall be called after cpu_clock_init().
This function is mainly used to lower power consumption.
*/
void cpu_clock_pll1_low_speed(void)
{
uint32_t pll_reg;
/* Configure PLL1 Clock (48MHz) */
/* Integer mode:
FCLKOUT = M*(FCLKIN/N)
FCCO = 2*P*FCLKOUT = 2*P*M*(FCLKIN/N)
*/
pll_reg = CGU_PLL1_CTRL;
/* Clear PLL1 bits */
pll_reg &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK | CGU_PLL1_CTRL_PD_MASK | CGU_PLL1_CTRL_FBSEL_MASK | /* CLK SEL, PowerDown , FBSEL */
CGU_PLL1_CTRL_BYPASS_MASK | /* BYPASS */
CGU_PLL1_CTRL_DIRECT_MASK | /* DIRECT */
CGU_PLL1_CTRL_PSEL_MASK | CGU_PLL1_CTRL_MSEL_MASK | CGU_PLL1_CTRL_NSEL_MASK ); /* PSEL, MSEL, NSEL- divider ratios */
/* Set PLL1 up to 12MHz * 4 = 48MHz. */
pll_reg |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL)
| CGU_PLL1_CTRL_PSEL(0)
| CGU_PLL1_CTRL_NSEL(0)
| CGU_PLL1_CTRL_MSEL(3)
| CGU_PLL1_CTRL_FBSEL(1)
| CGU_PLL1_CTRL_DIRECT(1);
CGU_PLL1_CTRL = pll_reg;
/* wait until stable */
while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK_MASK));
/* Wait a delay after switch to new frequency with Direct mode */
delay(WAIT_CPU_CLOCK_INIT_DELAY);
}
/*
Configure PLL1 (Main MCU Clock) to max speed (204MHz).
Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1.
This function shall be called after cpu_clock_init().
*/
void cpu_clock_pll1_max_speed(void)
{
uint32_t pll_reg;
/* Configure PLL1 to Intermediate Clock (between 90 MHz and 110 MHz) */
/* Integer mode:
FCLKOUT = M*(FCLKIN/N)
FCCO = 2*P*FCLKOUT = 2*P*M*(FCLKIN/N)
*/
pll_reg = CGU_PLL1_CTRL;
/* Clear PLL1 bits */
pll_reg &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK | CGU_PLL1_CTRL_PD_MASK | CGU_PLL1_CTRL_FBSEL_MASK | /* CLK SEL, PowerDown , FBSEL */
CGU_PLL1_CTRL_BYPASS_MASK | /* BYPASS */
CGU_PLL1_CTRL_DIRECT_MASK | /* DIRECT */
CGU_PLL1_CTRL_PSEL_MASK | CGU_PLL1_CTRL_MSEL_MASK | CGU_PLL1_CTRL_NSEL_MASK ); /* PSEL, MSEL, NSEL- divider ratios */
/* Set PLL1 up to 12MHz * 8 = 96MHz. */
pll_reg |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL)
| CGU_PLL1_CTRL_PSEL(0)
| CGU_PLL1_CTRL_NSEL(0)
| CGU_PLL1_CTRL_MSEL(7)
| CGU_PLL1_CTRL_FBSEL(1);
CGU_PLL1_CTRL = pll_reg;
/* wait until stable */
while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK_MASK));
/* Wait before to switch to max speed */
delay(WAIT_CPU_CLOCK_INIT_DELAY);
/* Configure PLL1 Max Speed */
/* Direct mode: FCLKOUT = FCCO = M*(FCLKIN/N) */
pll_reg = CGU_PLL1_CTRL;
/* Clear PLL1 bits */
pll_reg &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK | CGU_PLL1_CTRL_PD_MASK | CGU_PLL1_CTRL_FBSEL_MASK | /* CLK SEL, PowerDown , FBSEL */
CGU_PLL1_CTRL_BYPASS_MASK | /* BYPASS */
CGU_PLL1_CTRL_DIRECT_MASK | /* DIRECT */
CGU_PLL1_CTRL_PSEL_MASK | CGU_PLL1_CTRL_MSEL_MASK | CGU_PLL1_CTRL_NSEL_MASK ); /* PSEL, MSEL, NSEL- divider ratios */
/* Set PLL1 up to 12MHz * 17 = 204MHz. */
pll_reg |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL)
| CGU_PLL1_CTRL_PSEL(0)
| CGU_PLL1_CTRL_NSEL(0)
| CGU_PLL1_CTRL_MSEL(16)
| CGU_PLL1_CTRL_FBSEL(1)
| CGU_PLL1_CTRL_DIRECT(1);
CGU_PLL1_CTRL = pll_reg;
/* wait until stable */
while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK_MASK));
}
void ssp1_set_mode_max2837(void) void ssp1_set_mode_max2837(void)
{ {
spi_bus_start(max2837.bus, &ssp_config_max2837); spi_bus_start(max2837.bus, &ssp_config_max2837);
@ -777,7 +740,7 @@ void pin_setup(void) {
* *
* LPC43xx pull-up and pull-down resistors are approximately 53K. * LPC43xx pull-up and pull-down resistors are approximately 53K.
*/ */
#ifdef USER_INTERFACE_PORTAPACK #ifdef HACKRF_ONE
scu_pinmux(SCU_PINMUX_PP_TMS, SCU_GPIO_PUP | SCU_CONF_FUNCTION0); scu_pinmux(SCU_PINMUX_PP_TMS, SCU_GPIO_PUP | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_PINMUX_PP_TDO, SCU_GPIO_PDN | SCU_CONF_FUNCTION0); scu_pinmux(SCU_PINMUX_PP_TDO, SCU_GPIO_PDN | SCU_CONF_FUNCTION0);
#endif #endif
@ -818,10 +781,6 @@ void pin_setup(void) {
/* Configure RF power supply (VAA) switch control signal as output */ /* Configure RF power supply (VAA) switch control signal as output */
gpio_output(&gpio_vaa_disable); gpio_output(&gpio_vaa_disable);
#ifndef USER_INTERFACE_PORTAPACK
#endif
#endif
#ifdef RAD1O #ifdef RAD1O
/* Safe state: start with VAA turned off: */ /* Safe state: start with VAA turned off: */
disable_rf_power(); disable_rf_power();

11
firmware/common/hackrf_core.h
View File

@ -77,16 +77,15 @@ extern "C"
/* GPIO Input PinMux */ /* GPIO Input PinMux */
#define SCU_PINMUX_BOOT0 (P1_1) /* GPIO0[8] on P1_1 */ #define SCU_PINMUX_BOOT0 (P1_1) /* GPIO0[8] on P1_1 */
#define SCU_PINMUX_BOOT1 (P1_2) /* GPIO0[9] on P1_2 */ #define SCU_PINMUX_BOOT1 (P1_2) /* GPIO0[9] on P1_2 */
#ifdef USER_INTERFACE_PORTAPACK #ifndef HACKRF_ONE
#define SCU_PINMUX_BOOT2 (P2_8) /* GPIO5[7] on P2_8 */
#define SCU_PINMUX_BOOT3 (P2_9) /* GPIO1[10] on P2_9 */
#endif
#define SCU_PINMUX_PP_LCD_TE (P2_3) /* GPIO5[3] on P2_3 */ #define SCU_PINMUX_PP_LCD_TE (P2_3) /* GPIO5[3] on P2_3 */
#define SCU_PINMUX_PP_LCD_RDX (P2_4) /* GPIO5[4] on P2_4 */ #define SCU_PINMUX_PP_LCD_RDX (P2_4) /* GPIO5[4] on P2_4 */
#define SCU_PINMUX_PP_UNUSED (P2_8) /* GPIO5[7] on P2_8 */ #define SCU_PINMUX_PP_UNUSED (P2_8) /* GPIO5[7] on P2_8 */
#define SCU_PINMUX_PP_LCD_WRX (P2_9) /* GPIO1[10] on P2_9 */ #define SCU_PINMUX_PP_LCD_WRX (P2_9) /* GPIO1[10] on P2_9 */
#define SCU_PINMUX_PP_DIR (P2_13) /* GPIO1[13] on P2_13 */ #define SCU_PINMUX_PP_DIR (P2_13) /* GPIO1[13] on P2_13 */
#else
#define SCU_PINMUX_BOOT2 (P2_8) /* GPIO5[7] on P2_8 */
#define SCU_PINMUX_BOOT3 (P2_9) /* GPIO1[10] on P2_9 */
#endif
/* USB peripheral */ /* USB peripheral */
#ifdef JAWBREAKER #ifdef JAWBREAKER
@ -283,8 +282,6 @@ extern jtag_t jtag_cpld;
extern i2c_bus_t i2c0; extern i2c_bus_t i2c0;
void cpu_clock_init(void); void cpu_clock_init(void);
void cpu_clock_pll1_low_speed(void);
void cpu_clock_pll1_max_speed(void);
void ssp1_set_mode_max2837(void); void ssp1_set_mode_max2837(void);
void ssp1_set_mode_max5864(void); void ssp1_set_mode_max5864(void);

8
firmware/common/rf_path.c
View File

@ -391,7 +391,7 @@ void rf_path_set_direction(rf_path_t* const rf_path, const rf_path_direction_t d
switchctrl_set(rf_path, rf_path->switchctrl); switchctrl_set(rf_path, rf_path->switchctrl);
hackrf_ui_setDirection(direction); hackrf_ui()->set_direction(direction);
} }
void rf_path_set_filter(rf_path_t* const rf_path, const rf_path_filter_t filter) { void rf_path_set_filter(rf_path_t* const rf_path, const rf_path_filter_t filter) {
@ -416,7 +416,7 @@ void rf_path_set_filter(rf_path_t* const rf_path, const rf_path_filter_t filter)
switchctrl_set(rf_path, rf_path->switchctrl); switchctrl_set(rf_path, rf_path->switchctrl);
hackrf_ui_setFilter(filter); hackrf_ui()->set_filter(filter);
} }
void rf_path_set_lna(rf_path_t* const rf_path, const uint_fast8_t enable) { void rf_path_set_lna(rf_path_t* const rf_path, const uint_fast8_t enable) {
@ -437,7 +437,7 @@ void rf_path_set_lna(rf_path_t* const rf_path, const uint_fast8_t enable) {
switchctrl_set(rf_path, rf_path->switchctrl); switchctrl_set(rf_path, rf_path->switchctrl);
hackrf_ui_setLNAPower(enable); hackrf_ui()->set_lna_power(enable);
} }
/* antenna port power control */ /* antenna port power control */
@ -450,5 +450,5 @@ void rf_path_set_antenna(rf_path_t* const rf_path, const uint_fast8_t enable) {
switchctrl_set(rf_path, rf_path->switchctrl); switchctrl_set(rf_path, rf_path->switchctrl);
hackrf_ui_setAntennaBias(enable); hackrf_ui()->set_antenna_bias(enable);
} }

4
firmware/common/tuning.c
View File

@ -115,8 +115,8 @@ bool set_freq(const uint64_t freq)
max2837_set_mode(&max2837, prior_max2837_mode); max2837_set_mode(&max2837, prior_max2837_mode);
if( success ) { if( success ) {
freq_cache = freq; freq_cache = freq;
hackrf_ui_setFrequency(freq); hackrf_ui()->set_frequency(freq);
#ifndef USER_INTERFACE_PORTAPACK #ifdef HACKRF_ONE
operacake_set_range(freq_mhz); operacake_set_range(freq_mhz);
#endif #endif
} }

61
firmware/hackrf_usb/ui_portapack.c → firmware/common/ui_portapack.c
View File

@ -30,8 +30,6 @@
#include <stddef.h> #include <stddef.h>
#ifdef USER_INTERFACE_PORTAPACK
/* Pixel data within a font or bitmap byte is "reversed": LSB is left-most pixel. */ /* Pixel data within a font or bitmap byte is "reversed": LSB is left-most pixel. */
static const uint8_t font_fixed_8x16_glyph_data[] = { static const uint8_t font_fixed_8x16_glyph_data[] = {
@ -1043,62 +1041,3 @@ const hackrf_ui_t* portapack_detect(void) {
return NULL; return NULL;
} }
} }
static const hackrf_ui_t* ui = NULL;
const hackrf_ui_t* hackrf_ui(void) {
return ui;
}
void hackrf_ui_init(void) {
ui = portapack_detect();
if( ui != NULL ) {
ui->init();
}
}
void hackrf_ui_setFrequency(uint64_t frequency) {
if( ui != NULL ) ui->set_frequency(frequency);
}
void hackrf_ui_setSampleRate(uint32_t sample_rate) {
if( ui != NULL ) ui->set_sample_rate(sample_rate);
}
void hackrf_ui_setDirection(const rf_path_direction_t direction) {
if( ui != NULL ) ui->set_direction(direction);
}
void hackrf_ui_setFilterBW(uint32_t bw) {
if( ui != NULL ) ui->set_filter_bw(bw);
}
void hackrf_ui_setLNAPower(bool lna_on) {
if( ui != NULL ) ui->set_lna_power(lna_on);
}
void hackrf_ui_setBBLNAGain(const uint32_t gain_db) {
if( ui != NULL ) ui->set_bb_lna_gain(gain_db);
}
void hackrf_ui_setBBVGAGain(const uint32_t gain_db) {
if( ui != NULL ) ui->set_bb_vga_gain(gain_db);
}
void hackrf_ui_setBBTXVGAGain(const uint32_t gain_db) {
if( ui != NULL ) ui->set_bb_tx_vga_gain(gain_db);
}
void hackrf_ui_setFirstIFFrequency(const uint64_t frequency) {
if( ui != NULL ) ui->set_first_if_frequency(frequency);
}
void hackrf_ui_setFilter(const rf_path_filter_t filter) {
if( ui != NULL ) ui->set_filter(filter);
}
void hackrf_ui_setAntennaBias(bool antenna_bias) {
if( ui != NULL ) ui->set_antenna_bias(antenna_bias);
}
#endif

2
firmware/hackrf_usb/ui_portapack.h → firmware/common/ui_portapack.h
View File

@ -56,4 +56,6 @@ typedef struct ui_font_t {
size_t data_stride; size_t data_stride;
} ui_font_t; } ui_font_t;
const hackrf_ui_t* portapack_detect(void);
#endif/*__UI_PORTAPACK_H__*/ #endif/*__UI_PORTAPACK_H__*/

104
firmware/common/ui_rad1o.c Normal file
View File

@ -0,0 +1,104 @@
/*
* Copyright 2019 Dominic Spill
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#include "hackrf-ui.h"
#include "ui_rad1o.h"
/* Weak functions from rad1o app */
void hackrf_ui_init(void) __attribute__((weak));
void hackrf_ui_setFrequency(uint64_t _freq) __attribute__((weak));
void hackrf_ui_setSampleRate(uint32_t _sample_rate) __attribute__((weak));
void hackrf_ui_setDirection(const rf_path_direction_t _direction) __attribute__((weak));
void hackrf_ui_setFilterBW(uint32_t bw) __attribute__((weak));
void hackrf_ui_setLNAPower(bool _lna_on) __attribute__((weak));
void hackrf_ui_setBBLNAGain(const uint32_t gain_db) __attribute__((weak));
void hackrf_ui_setBBVGAGain(const uint32_t gain_db) __attribute__((weak));
void hackrf_ui_setBBTXVGAGain(const uint32_t gain_db) __attribute__((weak));
void hackrf_ui_setFirstIFFrequency(const uint64_t freq) __attribute__((weak));
void hackrf_ui_setFilter(const rf_path_filter_t filter) __attribute__((weak));
void hackrf_ui_setAntennaBias(bool antenna_bias) __attribute__((weak));
static void rad1o_ui_init(void) {
hackrf_ui_init();
}
static void rad1o_ui_set_frequency(uint64_t frequency) {
hackrf_ui_setFrequency(frequency);
}
static void rad1o_ui_set_sample_rate(uint32_t sample_rate) {
hackrf_ui_setSampleRate(sample_rate);
}
static void rad1o_ui_set_direction(const rf_path_direction_t direction) {
hackrf_ui_setDirection(direction);
}
static void rad1o_ui_set_filter_bw(uint32_t bandwidth) {
hackrf_ui_setFilterBW(bandwidth);
}
static void rad1o_ui_set_lna_power(bool lna_on) {
hackrf_ui_setLNAPower(lna_on);
}
static void rad1o_ui_set_bb_lna_gain(const uint32_t gain_db) {
hackrf_ui_setBBLNAGain(gain_db);
}
static void rad1o_ui_set_bb_vga_gain(const uint32_t gain_db) {
hackrf_ui_setBBVGAGain(gain_db);
}
static void rad1o_ui_set_bb_tx_vga_gain(const uint32_t gain_db) {
hackrf_ui_setBBTXVGAGain(gain_db);
}
static void rad1o_ui_set_first_if_frequency(const uint64_t frequency) {
hackrf_ui_setFirstIFFrequency(frequency);
}
static void rad1o_ui_set_filter(const rf_path_filter_t filter) {
hackrf_ui_setFilter(filter);
}
static void rad1o_ui_set_antenna_bias(bool antenna_bias) {
hackrf_ui_setAntennaBias(antenna_bias);
}
static const hackrf_ui_t rad1o_ui = {
&rad1o_ui_init,
&rad1o_ui_set_frequency,
&rad1o_ui_set_sample_rate,
&rad1o_ui_set_direction,
&rad1o_ui_set_filter_bw,
&rad1o_ui_set_lna_power,
&rad1o_ui_set_bb_lna_gain,
&rad1o_ui_set_bb_vga_gain,
&rad1o_ui_set_bb_tx_vga_gain,
&rad1o_ui_set_first_if_frequency,
&rad1o_ui_set_filter,
&rad1o_ui_set_antenna_bias,
};
const hackrf_ui_t* rad1o_ui_setup(void) {
return &rad1o_ui;
}

27
firmware/common/ui_rad1o.h Normal file
View File

@ -0,0 +1,27 @@
/*
* Copyright 2019 Dominic Spill
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#ifndef __UI_RAD1O_H__
#define __UI_RAD1O_H__
const hackrf_ui_t* rad1o_ui_setup(void);
#endif/*__UI_RAD1O_H__*/

16
firmware/hackrf-common.cmake
View File

@ -71,19 +71,11 @@ else()
set(MCU_PARTNO LPC4330) set(MCU_PARTNO LPC4330)
endif() endif()
if(BOARD STREQUAL "RAD1O")
set(USER_INTERFACE RAD1O)
endif()
if(NOT DEFINED USER_INTERFACE)
set(USER_INTERFACE NONE)
endif()
if(NOT DEFINED SRC_M0) if(NOT DEFINED SRC_M0)
set(SRC_M0 "${PATH_HACKRF_FIRMWARE_COMMON}/m0_sleep.c") set(SRC_M0 "${PATH_HACKRF_FIRMWARE_COMMON}/m0_sleep.c")
endif() endif()
SET(HACKRF_OPTS "-D${BOARD} -DUSER_INTERFACE_${USER_INTERFACE} -DLPC43XX -D${MCU_PARTNO} -DTX_ENABLE -D'VERSION_STRING=\"${VERSION}\"'") SET(HACKRF_OPTS "-D${BOARD} -DLPC43XX -D${MCU_PARTNO} -DTX_ENABLE -D'VERSION_STRING=\"${VERSION}\"'")
SET(LDSCRIPT_M4 "-T${PATH_HACKRF_FIRMWARE_COMMON}/${MCU_PARTNO}_M4_memory.ld -Tlibopencm3_lpc43xx_rom_to_ram.ld -T${PATH_HACKRF_FIRMWARE_COMMON}/LPC43xx_M4_M0_image_from_text.ld") SET(LDSCRIPT_M4 "-T${PATH_HACKRF_FIRMWARE_COMMON}/${MCU_PARTNO}_M4_memory.ld -Tlibopencm3_lpc43xx_rom_to_ram.ld -T${PATH_HACKRF_FIRMWARE_COMMON}/LPC43xx_M4_M0_image_from_text.ld")
@ -108,10 +100,7 @@ SET(CFLAGS_M4 "-std=gnu99 ${CFLAGS_COMMON} ${CPUFLAGS_M4} -DLPC43XX_M4")
SET(CXXFLAGS_M4 "-std=gnu++0x ${CFLAGS_COMMON} ${CPUFLAGS_M4} -DLPC43XX_M4") SET(CXXFLAGS_M4 "-std=gnu++0x ${CFLAGS_COMMON} ${CPUFLAGS_M4} -DLPC43XX_M4")
SET(LDFLAGS_M4 "${LDFLAGS_COMMON} ${CPUFLAGS_M4} ${LDSCRIPT_M4} -Xlinker -Map=m4.map") SET(LDFLAGS_M4 "${LDFLAGS_COMMON} ${CPUFLAGS_M4} ${LDSCRIPT_M4} -Xlinker -Map=m4.map")
SET(CFLAGS_M4_DFU "-std=gnu99 ${CFLAGS_COMMON} ${CPUFLAGS_M4} -DLPC43XX_M4") SET(CFLAGS_M4_DFU "-std=gnu99 ${CFLAGS_COMMON} ${CPUFLAGS_M4} -DLPC43XX_M4 -DDFU_MODE")
if(NOT USER_INTERFACE STREQUAL "PORTAPACK")
SET(CFLAGS_M4_DFU "${CFLAGS_M4_DFU} -DDFU_MODE")
endif()
SET(LDFLAGS_M4_DFU "${LDFLAGS_COMMON} ${CPUFLAGS_M4} ${LDSCRIPT_M4_DFU} -Xlinker -Map=m4.map") SET(LDFLAGS_M4_DFU "${LDFLAGS_COMMON} ${CPUFLAGS_M4} ${LDSCRIPT_M4_DFU} -Xlinker -Map=m4.map")
set(BUILD_SHARED_LIBS OFF) set(BUILD_SHARED_LIBS OFF)
@ -138,6 +127,7 @@ macro(DeclareTargets)
${PATH_HACKRF_FIRMWARE_COMMON}/spi_bus.c ${PATH_HACKRF_FIRMWARE_COMMON}/spi_bus.c
${PATH_HACKRF_FIRMWARE_COMMON}/spi_ssp.c ${PATH_HACKRF_FIRMWARE_COMMON}/spi_ssp.c
${PATH_HACKRF_FIRMWARE_COMMON}/gpio_lpc.c ${PATH_HACKRF_FIRMWARE_COMMON}/gpio_lpc.c
${PATH_HACKRF_FIRMWARE_COMMON}/hackrf-ui.c
) )
if(BOARD STREQUAL "RAD1O") if(BOARD STREQUAL "RAD1O")

13
firmware/hackrf_usb/CMakeLists.txt
View File

@ -48,18 +48,25 @@ set(SRC_M4
"${PATH_HACKRF_FIRMWARE_COMMON}/fault_handler.c" "${PATH_HACKRF_FIRMWARE_COMMON}/fault_handler.c"
"${PATH_HACKRF_FIRMWARE_COMMON}/cpld_jtag.c" "${PATH_HACKRF_FIRMWARE_COMMON}/cpld_jtag.c"
"${PATH_HACKRF_FIRMWARE_COMMON}/cpld_xc2c.c" "${PATH_HACKRF_FIRMWARE_COMMON}/cpld_xc2c.c"
"${PATH_HACKRF_FIRMWARE_COMMON}/crc.c"
"${PATH_HACKRF_FIRMWARE_COMMON}/xapp058/lenval.c" "${PATH_HACKRF_FIRMWARE_COMMON}/xapp058/lenval.c"
"${PATH_HACKRF_FIRMWARE_COMMON}/xapp058/micro.c" "${PATH_HACKRF_FIRMWARE_COMMON}/xapp058/micro.c"
"${PATH_HACKRF_FIRMWARE_COMMON}/xapp058/ports.c" "${PATH_HACKRF_FIRMWARE_COMMON}/xapp058/ports.c"
"${PATH_HACKRF_FIRMWARE_COMMON}/crc.c"
"${PATH_HACKRF_FIRMWARE_COMMON}/rom_iap.c" "${PATH_HACKRF_FIRMWARE_COMMON}/rom_iap.c"
"${PATH_HACKRF_FIRMWARE_COMMON}/operacake.c" "${PATH_HACKRF_FIRMWARE_COMMON}/operacake.c"
) )
if(USER_INTERFACE STREQUAL "PORTAPACK") if(BOARD STREQUAL "HACKRF_ONE")
SET(SRC_M4 SET(SRC_M4
${SRC_M4} ${SRC_M4}
ui_portapack.c "${PATH_HACKRF_FIRMWARE_COMMON}/ui_portapack.c"
)
endif()
if(BOARD STREQUAL "RAD1O")
SET(SRC_M4
${SRC_M4}
"${PATH_HACKRF_FIRMWARE_COMMON}/ui_rad1o.c"
) )
endif() endif()

8
firmware/hackrf_usb/hackrf_usb.c
View File

@ -139,7 +139,11 @@ static usb_request_handler_fn vendor_request_handler[] = {
usb_vendor_request_spiflash_status, usb_vendor_request_spiflash_status,
usb_vendor_request_spiflash_clear_status, usb_vendor_request_spiflash_clear_status,
usb_vendor_request_operacake_gpio_test, usb_vendor_request_operacake_gpio_test,
#ifdef HACKRF_ONE
usb_vendor_request_cpld_checksum, usb_vendor_request_cpld_checksum,
#else
NULL,
#endif
}; };
static const uint32_t vendor_request_handler_count = static const uint32_t vendor_request_handler_count =
@ -175,11 +179,9 @@ void usb_configuration_changed(
set_transceiver_mode(TRANSCEIVER_MODE_OFF); set_transceiver_mode(TRANSCEIVER_MODE_OFF);
if( device->configuration->number == 1 ) { if( device->configuration->number == 1 ) {
// transceiver configuration // transceiver configuration
cpu_clock_pll1_max_speed();
led_on(LED1); led_on(LED1);
} else { } else {
/* Configuration number equal 0 means usb bus reset. */ /* Configuration number equal 0 means usb bus reset. */
cpu_clock_pll1_low_speed();
led_off(LED1); led_off(LED1);
} }
} }
@ -239,7 +241,7 @@ int main(void) {
nvic_set_priority(NVIC_USB0_IRQ, 255); nvic_set_priority(NVIC_USB0_IRQ, 255);
hackrf_ui_init(); hackrf_ui()->init();
usb_run(&usb_device); usb_run(&usb_device);

6
firmware/hackrf_usb/usb_api_transceiver.c
View File

@ -153,7 +153,7 @@ usb_request_status_t usb_vendor_request_set_lna_gain(
if( stage == USB_TRANSFER_STAGE_SETUP ) { if( stage == USB_TRANSFER_STAGE_SETUP ) {
const uint8_t value = max2837_set_lna_gain(&max2837, endpoint->setup.index); const uint8_t value = max2837_set_lna_gain(&max2837, endpoint->setup.index);
endpoint->buffer[0] = value; endpoint->buffer[0] = value;
if(value) hackrf_ui_setBBLNAGain(endpoint->setup.index); if(value) hackrf_ui()->set_bb_lna_gain(endpoint->setup.index);
usb_transfer_schedule_block(endpoint->in, &endpoint->buffer, 1, usb_transfer_schedule_block(endpoint->in, &endpoint->buffer, 1,
NULL, NULL); NULL, NULL);
usb_transfer_schedule_ack(endpoint->out); usb_transfer_schedule_ack(endpoint->out);
@ -168,7 +168,7 @@ usb_request_status_t usb_vendor_request_set_vga_gain(
if( stage == USB_TRANSFER_STAGE_SETUP ) { if( stage == USB_TRANSFER_STAGE_SETUP ) {
const uint8_t value = max2837_set_vga_gain(&max2837, endpoint->setup.index); const uint8_t value = max2837_set_vga_gain(&max2837, endpoint->setup.index);
endpoint->buffer[0] = value; endpoint->buffer[0] = value;
if(value) hackrf_ui_setBBVGAGain(endpoint->setup.index); if(value) hackrf_ui()->set_bb_vga_gain(endpoint->setup.index);
usb_transfer_schedule_block(endpoint->in, &endpoint->buffer, 1, usb_transfer_schedule_block(endpoint->in, &endpoint->buffer, 1,
NULL, NULL); NULL, NULL);
usb_transfer_schedule_ack(endpoint->out); usb_transfer_schedule_ack(endpoint->out);
@ -183,7 +183,7 @@ usb_request_status_t usb_vendor_request_set_txvga_gain(
if( stage == USB_TRANSFER_STAGE_SETUP ) { if( stage == USB_TRANSFER_STAGE_SETUP ) {
const uint8_t value = max2837_set_txvga_gain(&max2837, endpoint->setup.index); const uint8_t value = max2837_set_txvga_gain(&max2837, endpoint->setup.index);
endpoint->buffer[0] = value; endpoint->buffer[0] = value;
if(value) hackrf_ui_setBBTXVGAGain(endpoint->setup.index); if(value) hackrf_ui()->set_bb_tx_vga_gain(endpoint->setup.index);
usb_transfer_schedule_block(endpoint->in, &endpoint->buffer, 1, usb_transfer_schedule_block(endpoint->in, &endpoint->buffer, 1,
NULL, NULL); NULL, NULL);
usb_transfer_schedule_ack(endpoint->out); usb_transfer_schedule_ack(endpoint->out);

7
tools/deploy-nightly.sh
View File

@ -1,10 +1,9 @@
#!/bin/bash #!/bin/bash
REPO=greatscottgadgets/hackrf-nightly
PUBLICATION_BRANCH=master PUBLICATION_BRANCH=master
# set -x # set -x
cd $HOME cd $HOME
# Checkout the branch # Checkout the branch
git clone --branch=$PUBLICATION_BRANCH https://${GITHUB_TOKEN}@github.com/$REPO.git publish git clone --branch=$PUBLICATION_BRANCH https://${GITHUB_TOKEN}@github.com/${ARTEFACT_REPO}.git publish
cd publish cd publish
# Update pages # Update pages
cp $ARTEFACT_BASE/$BUILD_NAME.tar.xz . cp $ARTEFACT_BASE/$BUILD_NAME.tar.xz .
@ -22,13 +21,11 @@ echo "
<h2>HackRF Nightly Builds</h2> <h2>HackRF Nightly Builds</h2>
" > index.html " > index.html
URL=https://greatscottgadgets.github.io/hackrf-nightly
for commit in $COMMITS; do for commit in $COMMITS; do
FILENAME=`find . -maxdepth 1 -name "*-$commit.tar.xz"` FILENAME=`find . -maxdepth 1 -name "*-$commit.tar.xz"`
if [ "$FILENAME" != "" ]; then if [ "$FILENAME" != "" ]; then
FN=${FILENAME:2} FN=${FILENAME:2}
echo "<a href=\"$URL/$FN\">$FN</a><br />" >> index.html echo "<a href=\"${ARTEFACT_URL}/$FN\">$FN</a><br />" >> index.html
fi fi
done done